8.1.1 External Components

The procedure for calculating the external components is illustrated with the following design example. The Bill of Materials for this design is listed in Table 1. The circuit shown in Functional Block Diagram is configured for the following specifications:

• V_OUT = 5 V
• V_IN = 7 V to 42 V
• Fs = 300 kHz
• Minimum load current (for CCM) = 100 mA
• Maximum load current = 0.5 A

8.1.2 R3 (R_T)

R_T sets the oscillator switching frequency. Generally, higher frequency applications are smaller but have higher losses. Operation at 300 kHz was selected for this example as a reasonable compromise for both small size and high efficiency. The value of R_T for 300 kHz switching frequency can be calculated in Equation 5:

Equation 5.

The nearest standard value of 21 kΩ was chosen for R_T.

8.1.3 L1

The inductor value is determined based on the operating frequency, load current, ripple current, and the minimum and maximum input voltage (V_IN(min), V_IN(max)).

Figure 14. Inductor Current Waveform

To keep the circuit in continuous conduction mode (CCM), the maximum ripple current I_RIPPLE should be less than twice the minimum load current, or 0.2 Ap-p. Using this value of ripple current, the value of inductor (L1) is calculated using the following:

Equation 6.

Equation 7.

This procedure provides a guide to select the value of L1. The nearest standard value (100 µH) will be used. L1 must be rated for the peak current (I_PK+) to prevent saturation. During normal loading conditions, the peak current occurs at maximum load current plus maximum ripple. During an overload condition the peak current is limited to 0.7 A nominal (0.85 A maximum). The selected inductor (see Table 1) has a conservative 1.0 Amp saturation current rating. For this manufacturer, the saturation rating is defined as the current necessary for the inductance to reduce by 30%, at 20°C.

8.1.4 C3 (C_RAMP)

With the inductor value selected, the value of C3 (C_RAMP) necessary for the emulation ramp circuit is:

Where L is in Henrys

With L1 selected for 100 µH the recommended value for C3 is 470 pF (nearest standard value).

8.1.5 C9

The output capacitor, C9 smoothes the inductor ripple current and provides a source of charge for transient loading conditions. For this design a 22 µF ceramic capacitor was selected. The ceramic capacitor provides ultra low ESR to reduce the output ripple voltage and noise spikes. An approximation for the output ripple voltage is:

Equation 9.

8.1.6 C1

The regulator supply voltage has a large source impedance at the switching frequency. Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current during the on-time. When the buck switch turns on, the current into the VIN pin steps to the lower peak of the inductor current waveform, ramps up to the peak value, then drops to zero at turn-off. The average current into VIN during the on-time is the load current. The input capacitance should be selected for RMS current rating and minimum ripple voltage. A good approximation for the required ripple current rating necessary is I_RMS > I_OUT / 2.

Quality ceramic capacitors with a low ESR should be selected for the input filter. To allow for capacitor tolerances and voltage effects, one 1.0 µF, 100 V ceramic capacitor will be used. If step input voltage transients are expected near the maximum rating of the LM25574-Q1, a careful evaluation of ringing and possible spikes at the device VIN pin should be completed. An additional damping network or input voltage clamp may be required in these cases.

8.1.7 C8

The capacitor at the VCC pin provides noise filtering and stability for the V_CC regulator. The recommended value of C8 should be no smaller than 0.1 µF, and should be a good quality, low ESR, ceramic capacitor. A value of 0.47 µF was selected for this design.

8.1.8 C7

The bootstrap capacitor between the BST and the SW pins supplies the gate current to charge the buck switch gate at turn-on. The recommended value of C7 is 0.022 µF, and should be a good quality, low ESR, ceramic capacitor.

8.1.9 C4

The capacitor at the SS pin determines the soft-start time, that is the time for the reference voltage and the output voltage, to reach the final regulated value. The time is determined from Equation 10:

Equation 10.

For this application, a C4 value of 0.01 µF was chosen which corresponds to a soft-start time of 1 ms.

8.1.10 R5, R6

R5 and R6 set the output voltage level, the ratio of these resistors is calculated from Equation 11:

For a 5 V output, the R5 and R6 ratio calculates to 3.082. The resistors should be chosen from standard value resistors, a good starting point is selection in the range of 1.0 kΩ - 10 kΩ. Values of 5.11 kΩ for R5, and 1.65 kΩ for R6 were selected.

8.1.11 R1, R2, C2

A voltage divider can be connected to the SD pin to set a minimum operating voltage V_IN(min) for the regulator. If this feature is required, the easiest approach to select the divider resistor values is to select a value for R1 (between 10 kΩ and 100 kΩ recommended) then calculate R2 from Equation 12:

Equation 12.

Capacitor C2 provides filtering for the divider. The voltage at the SD pin should never exceed 8 V, when using an external set-point divider it may be necessary to clamp the SD pin at high input voltage conditions. The reference design utilizes the full range of the LM25574-Q1 (6 V to 42 V); therefore these components can be omitted. With the SD pin open circuit the LM25574-Q1 responds once the V_CC UVLO threshold is satisfied.

8.1.12 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator gain of the LM25574-Q1 is as follows:

The dominant low frequency pole of the modulator is determined by the load resistance (R_LOAD,) and output capacitance (C_OUT). The corner frequency of this pole is:

For R_LOAD = 20 Ω and C_OUT = 22 µF then f_p(MOD) = 362 Hz

DC Gain_(MOD) = 0.5 x 20 = 20 dB

For the design example of Functional Block Diagram the following modulator gain vs. frequency characteristic was measured as shown in Figure 15.

Figure 15. Gain and Phase of Modulator R_LOAD = 20 Ohms and C_OUT = 22µF

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a zero at f_Z = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 25 kHz was selected. The compensation network zero (f_Z) should be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4 C5) to be less than 2 kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was selected for 0.022 µF and R4 was selected for 24.9 kΩ. These values configure the compensation network zero at 290 Hz. The error amp gain at frequencies greater than f_Z is: R4 / R5, which is approximately 5 (14 dB).

Figure 16. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

Figure 17. Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small since the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C6 is: f_p2 = fz x C5 / C6.

8.1.13 Bias Power Dissipation Reduction

Buck regulators operating with high input voltage can dissipate an appreciable amount of power for the bias of the IC. The V_CC regulator must step-down the input voltage V_IN to a nominal V_CC level of 7 V. The large voltage drop across the V_CC regulator translates into a large power dissipation within the V_CC regulator. There are several techniques that can significantly reduce this bias regulator power dissipation. Figure 18 and Figure 19 depict two methods to bias the IC from the output voltage. In each case the internal V_CC regulator is used to initially bias the VCC pin. After the output voltage is established, the VCC pin potential is raised above the nominal 7 V regulation level, which effectively disables the internal V_CC regulator. The voltage applied to the VCC pin should never exceed 14 V. The V_CC voltage should never be larger than the V_IN voltage.

Figure 18. VCC Bias from VOUT for 8 V < VOUT < 14 V

Figure 19. VCC Bias with Additional Winding on the Output Inductor

8.2.1 Typical Schematic for High Frequency (1 MHz) Application