SNVS443C May   2006  – December 2016 LM3489 , LM3489-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM3489
    3. 6.3 ESD Ratings: LM3489-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hysteretic Control Circuit
        1. 7.3.1.1 Delay
      2. 7.3.2 Current Limit Operation
      3. 7.3.3 Start Up
      4. 7.3.4 External Sense Resistor
      5. 7.3.5 PGATE
      6. 7.3.6 Adjustable UVLO
    4. 7.4 Device Functional Mode
      1. 7.4.1 Device Enable and Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection (L)
        2. 8.2.2.2 Output Capacitor Selection (COUT)
        3. 8.2.2.3 Input Capacitor Selection (CIN)
        4. 8.2.2.4 Programming the Current Limit (RADJ)
        5. 8.2.2.5 Catch Diode Selection (D1)
        6. 8.2.2.6 P-Channel MOSFET Selection (Q1)
        7. 8.2.2.7 Interfacing With the Enable Pin
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

The PCB layout is very important in all switching regulator designs. Poor layout can cause switching noise into the feedback signal and generate EMI problems. For minimal inductance, the wires indicated by heavy lines in schematic diagram must be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the anode of the catch diode. This path carries a large AC current. The switching node, the node with the diode cathode, inductor and FET drain must be kept short. This node is one of the main sources for radiated EMI since it sees a large AC voltage at the switching frequency. It is always a good practice to use a ground plane in the design, particularly for high-current applications.

The two ground pins, PGND and GND, must be connected by as short a trace as possible. They can be connected underneath the device. These pins are resistively connected internally by approximately 50 Ω. The ground pins must be tied to the ground plane, or to a large ground trace in close proximity to both the FB divider and COUT grounds.

The gate pin of the external PFET must be placed close to the PGATE pin. However, if a very small FET is used, a resistor may be required between PGATE pin and the gate of the PFET to reduce high-frequency ringing. Because this resistor will slow down the PFET’s rise time, the current limit blanking time must be taken into consideration (see Current Limit Operation). The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling with the inductor or the switching node. The FB trace must be kept away from those areas. Also, the orientation of the inductor can contribute un-wanted noise coupling to the FB path. If noise problems are observed it may be worth trying a different orientation of the inductor and select the best for final component placement.

Layout Examples

SPACE

LM3489 LM3489-Q1 20191503.png Figure 30. LM3489 EVM PCB Top Layer Layout
LM3489 LM3489-Q1 20191504.png Figure 31. LM3489 EVM PCB Bottom Layer Layout