SNVS443C May   2006  – December 2016 LM3489 , LM3489-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings: LM3489
    3. 6.3 ESD Ratings: LM3489-Q1
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hysteretic Control Circuit
        1. 7.3.1.1 Delay
      2. 7.3.2 Current Limit Operation
      3. 7.3.3 Start Up
      4. 7.3.4 External Sense Resistor
      5. 7.3.5 PGATE
      6. 7.3.6 Adjustable UVLO
    4. 7.4 Device Functional Mode
      1. 7.4.1 Device Enable and Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection (L)
        2. 8.2.2.2 Output Capacitor Selection (COUT)
        3. 8.2.2.3 Input Capacitor Selection (CIN)
        4. 8.2.2.4 Programming the Current Limit (RADJ)
        5. 8.2.2.5 Catch Diode Selection (D1)
        6. 8.2.2.6 P-Channel MOSFET Selection (Q1)
        7. 8.2.2.7 Interfacing With the Enable Pin
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Hysteretic control is a simple control scheme. However the operating frequency and other performance characteristics highly depend on external conditions and components. If either the inductance, output capacitance, ESR, VIN, or Cff is changed, there is a change in the operating frequency and output ripple. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and COUT ESR.

Typical Application

LM3489 LM3489-Q1 20186953.gif Figure 25. Typical Application Schematic for VOUT = 3.3 V, 500 mA

Design Requirements

The important parameters for the inductor are the inductance and the current rating. The LM3489 operates over a wide frequency range and can use a wide range of inductance values. A rule of thumb is to use the equations used for Simple Switchers®. The equations for inductor ripple (Δi) as a function of output current (IOUT) depend on Iout:

For Iout < 2 A, Δi ≤ Iout × Iout−0.366726.

For Iout > 2 A, Δi ≤ Iout × 0.3.

Detailed Design Procedure

Inductor Selection (L)

The inductance can be calculated with Equation 9 and Equation 10 based upon the desired operating frequency.

Equation 9. LM3489 LM3489-Q1 20186932.gif
Equation 10. LM3489 LM3489-Q1 20186933.gif

where

  • D is the duty cycle
  • VD is the diode forward voltage
  • VDS is the voltage drop across the PFET

The inductor must be rated with Equation 11.

Equation 11. LM3489 LM3489-Q1 20186950.gif

The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. The second is the inductor ESR that contribute to the steady-state power loss due to current flowing through the inductor.

Output Capacitor Selection (COUT)

The ESR of the output capacitor times the inductor ripple current is equal to the output ripple of the regulator. However, the VHYST sets the first-order value of this ripple. As ESR is increased with a given inductance, operating frequency increases as well. If ESR is reduced then the operating frequency reduces.

The use of ceramic capacitors has become a common desire of many power supply designers. However, ceramic capacitors have a very low ESR resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low-value resistor must be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provides highly accurate control over the output voltage ripple. Other types capacitor, such as Sanyo POS CAP and OS-CON, Panasonic SP CAP, and Nichicon NA series, are also recommended and may be used without additional series resistance.

For all practical purposes, any type of output capacitor may be used with proper circuit verification.

Input Capacitor Selection (CIN)

A bypass capacitor is required between the input source and ground. It must be located near the source pin of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on.

The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer's recommended voltage derating. For high-input voltage applications, low-ESR electrolytic, Nichicon UD series or the Panasonic FK series are available. The RMS current in the input capacitor can be calculated with Equation 12.

Equation 12. LM3489 LM3489-Q1 20186934.gif

The input capacitor power dissipation can be calculated with Equation 13.

Equation 13. PD(CIN) = IRMS_CIN2 × ESRCIN

The input capacitor must be able to handle the RMS current and the dissipation. Several input capacitors may be connected in parallel to handle large RMS currents. In some cases it may be much cheaper to use multiple electrolytic capacitors than a single low-ESR, high-performance capacitor such as OS-CON or Tantalum. The capacitance value must be selected such that the ripple voltage created by the switch current pulses is less than 10% of the total DC voltage across the capacitor.

For high VIN conditions (> 28 V), the fast switching, high swing of the internal gate drive introduces unwanted disturbance to the VIN rail and the current limit function can be affected. To eliminate this potential problem, a high-quality ceramic capacitor of 0.1 µF is recommended to filter out the internal disturbance at the VIN pin. This capacitor must be placed right next to the VIN pin for best performance.

Programming the Current Limit (RADJ)

The current limit is determined with Equation 14 by connecting a resistor (RADJ) between input voltage and the ADJ pin, pin 5.

Equation 14. LM3489 LM3489-Q1 20186935.gif

where

  • RDSON is Drain-Source ON resistance of the external PFET
  • ICL_ADJ is 3 µA minimum
  • IIND_PEAK = ILOAD + IRIPPLE / 2

Using the minimum value for ICL_ADJ (3 µA) ensures that the current limit threshold is set higher than the peak inductor current.

The RADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5 V. With this in mind, RADJ_MAX = (VIN – 3.5) / 7 µA. If a larger RADJ value is needed to set the desired current limit, either use a PFET with a lower RDSON or use a current sense resistor as shown in Figure 23.

The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.

Catch Diode Selection (D1)

The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average power dissipation. The average current through the diode can be calculated with Equation 15.

Equation 15. ID_AVE = IOUT × (1 – D)

The off-state voltage across the catch diode is approximately equal to the input voltage. The peak reverse voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low-output voltage applications, a low forward voltage provides improved efficiency. For high-temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.

P-Channel MOSFET Selection (Q1)

The important parameters for the PFET are the maximum Drain-Source voltage (VDS), the ON resistance (RDSON), Current rating, and the input capacitance.

The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the input voltage.

PFET drain current, Id, must be rated higher than the peak inductor current, IIND-PEAK.

Depending on operating conditions, the PGATE voltage may fall as low as VIN – 8.3 V. Therefore, a PFET must be selected with a VGS maximum rating greater than the maximum PGATE swing voltage.

As input voltage decreases below 9 V, PGATE swing voltage may also decrease. At 5-V input the PGATE will swing from VIN to VIN – 4.6 V. To ensure that the PFET turns on quickly and completely, a low threshold PFET must be used when the input voltage is less than 7 V.

Total power loss in the FET can be approximated using Equation 16.

Equation 16. PDswitch = RDSON × IOUT2× D + F × IOUT × VIN × (ton + toff) / 2

where

  • ton is the FET turn on time
  • toff is the FET turn off time

A value of 10 ns to 20 ns is typical for ton and toff.

A PFET must be selected with a turnon rise time of less than 100 ns. Slower rise times will degrade efficiency, can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.

The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher than the 25°C value. This increase in RDSON must be considered when determining RADJ in wide temperature range applications. If the current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.

Keeping the gate capacitance below 2000 pF is recommended to keep switching losses and transition times low. This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation within the controller.

As gate capacitance increases, operating frequency must be reduced and as gate capacitance decreases operating frequency can be increased.

Interfacing With the Enable Pin

The enable pin is internally pulled high with clamping at 8 V typical. For normal operation this pin must be left open. To disable the device, the enable pin must be connected to ground externally. If an external voltage source is applied to this pin for enable control, the applied voltage must not exceed the maximum operating voltage level specified in this datasheet, that is 5.5 V. For most applications, an open-drain or open-collector transistor can be used to short this pin to ground to shutdown the device .

Application Curves

LM3489 LM3489-Q1 20186913.gif
VOUT = 3.3 V, L = 22 µH
Figure 26. Efficiency vs Load Current
LM3489 LM3489-Q1 20186957.png
No load, CADJ = 1 nF
Figure 28. Power Up
LM3489 LM3489-Q1 20186942.gif
VOUT = 3.3 V, L = 22 µH
Figure 27. VOUT Regulation vs Load Current
LM3489 LM3489-Q1 20186954.png
VOUT = 3.3 V, 50 mA to 500 mA load
Figure 29. Load Transient