SNVS428H January 2006 – October 2015 LM5035
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | APPLICATION INFORMATION | ||
---|---|---|---|---|---|
NAME | NO. | ||||
HTSSOP | WQFN | ||||
AGND | 6 | 5 | GND | Analog ground | Connect directly to Power Ground. |
COMP | 4 | 3 | I/O | Input to the pulse width modulator | An external optocoupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the optocoupler detector. |
CS | 7 | 6 | I | Current sense input for current limit | If CS exceeds 0.25 V, the output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 50 ns after HO or LO switches high to blank leading edge transients. |
DLY | 9 | 8 | I | Timing programming pin for the LO and HO to SR1 and SR2 outputs | An external resistor to ground sets the timing for the nonoverlap time of HO to SR1 and LO to SR2. |
HB | 11 | 11 | I/O | Boost voltage for the HO driver | An external diode is required from VCC to HB and an external capacitor is required from HS to HB to power the HO gate driver. |
HO | 13 | 13 | O | High side gate drive output | Output of the high side PWM gate driver. Capable of sinking 2-A peak current. |
HS | 12 | 12 | I/O | Switch node | Connection common to the transformer and both power switches. Provides a return path for the HO gate driver. |
LO | 14 | 14 | O | Low side gate drive output | Output of the low side PWM gate driver. Capable of sinking 2-A peak current. |
NC | 1, 10, 20, 22 | — | No connection | No electrical contact. | |
OVP | 3 | 2 | I | Line overvoltage protection | An external voltage divider from the power source sets the shutdown levels. The threshold is 1.25 V. Hysteresis is set by an internal current source that sources 23 µA into the external resistor divider. |
PGND | 15 | 15 | GND | Power ground | Connect directly to Analog Ground. |
RAMP | 1 | 23 | I | Modulator ramp signal | An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt Second clamp comparator. |
REF | 19 | 19 | O | Output of 5-V reference | Maximum output current is 20 mA. Locally decoupled with a 0.1-µF capacitor. |
RT | 5 | 4 | I | Oscillator frequency control and sync clock input | Normally biased at 2 V. An external resistor connected between RT and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. |
RES | 10 | 9 | I | Restart timer | If cycle-by-cycle current limit is exceeded during any cycle, a 22-µA current is sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start capacitor will be fully discharged and then released with a pull-up current of 1.2 µA. After the first output pulse at LO (when SS > COMP offset, typically 1 V), the SS pin charging current will revert to 55 µA. |
SR1 | 18 | 18 | O | Synchronous rectifier driver output | Control output of the synchronous FET gate. Capable of 0.5-A peak current. |
SR2 | 17 | 17 | O | Synchronous rectifier driver output | Control output of the synchronous FET gate. Capable of 0.5-A peak current. |
SS | 8 | 7 | I | Soft-start input | An internal 55-µA current source charges an external capacitor to set the soft-start rate. During a current limit restart sequence, the internal current source is reduced to 1.2 µA to increase the delay before retry. |
UVLO | 2 | 24 | I | Line undervoltage lockout | An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25-V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current sink that pulls 23 µA from the external resistor divider. |
VCC | 16 | 16 | I/O | Output of the high voltage start-up regulator. The VCC voltage is regulated to 7.6 V | If an auxiliary winding raises the voltage on this pin above the regulation set-point, the start-up regulator will shutdown, thus reducing the internal power dissipation. |
VIN | 20 | 21 | I | Input voltage source | Input to the Start-up Regulator. Operating input range is 13 V to 100 V with transient capability to 105 V. For power sources outside of this range, the LM5035 can be biased directly at VCC by an external regulator. |
EP | GND | Exposed pad, underside of package (WQFN) | No electrical contact. Connect to system ground plane for reduced thermal resistance. | ||
PowerPAD (HTSSOP) |