SNVS950C April   2014  – July 2016 LM5066I

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SMBus Communications Timing Requirements and Definitions
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Current Limit
      2. 8.3.2 Circuit Breaker
      3. 8.3.3 Power Limit
      4. 8.3.4 UVLO
      5. 8.3.5 OVLO
      6. 8.3.6 Power Good Pin
      7. 8.3.7 VDD Sub-Regulator
      8. 8.3.8 Remote Temperature Sensing
      9. 8.3.9 Damaged MOSFET Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up Sequence
      2. 8.4.2 Gate Control
      3. 8.4.3 Fault Timer and Restart
      4. 8.4.4 Shutdown Control
      5. 8.4.5 Enabling/Disabling and Resetting
    5. 8.5 Programming
      1. 8.5.1 PMBus Command Support
      2. 8.5.2 Standard PMBus Commands
        1. 8.5.2.1  OPERATION (01h)
        2. 8.5.2.2  CLEAR_FAULTS (03h)
        3. 8.5.2.3  CAPABILITY (19h)
        4. 8.5.2.4  VOUT_UV_WARN_LIMIT (43h)
        5. 8.5.2.5  OT_FAULT_LIMIT (4Fh)
        6. 8.5.2.6  OT_WARN_LIMIT (51h)
        7. 8.5.2.7  VIN_OV_WARN_LIMIT (57h)
        8. 8.5.2.8  VIN_UV_WARN_LIMIT (58h)
        9. 8.5.2.9  STATUS_BYTE (78h)
        10. 8.5.2.10 STATUS_WORD (79h)
        11. 8.5.2.11 STATUS_VOUT (7Ah)
        12. 8.5.2.12 STATUS_INPUT (7Ch)
        13. 8.5.2.13 STATUS_TEMPERATURE (7dh)
        14. 8.5.2.14 STATUS_CML (7Eh)
        15. 8.5.2.15 STATUS_OTHER (7Fh)
        16. 8.5.2.16 STATUS_MFR_SPECIFIC (80h)
        17. 8.5.2.17 READ_EIN (86h)
        18. 8.5.2.18 READ_VIN (88h)
        19. 8.5.2.19 READ_IIN (89h)
        20. 8.5.2.20 READ_VOUT (8Bh)
        21. 8.5.2.21 READ_TEMPERATURE_1 (8Dh)
        22. 8.5.2.22 READ_PIN (97h)
        23. 8.5.2.23 MFR_ID (99h)
        24. 8.5.2.24 MFR_MODEL (9Ah)
        25. 8.5.2.25 MFR_REVISION (9Bh)
      3. 8.5.3 Manufacturer Specific PMBus Commands
        1. 8.5.3.1  MFR_SPECIFIC_00: READ_VAUX (D0h)
        2. 8.5.3.2  MFR_SPECIFIC_01: MFR_READ_IIN (D1h)
        3. 8.5.3.3  MFR_SPECIFIC_02: MFR_READ_PIN (D2h)
        4. 8.5.3.4  MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h)
        5. 8.5.3.5  MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h)
        6. 8.5.3.6  MFR_SPECIFIC_05: READ_PIN_PEAK (D5h)
        7. 8.5.3.7  MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h)
        8. 8.5.3.8  MFR_SPECIFIC_07: GATE_MASK (D7h)
        9. 8.5.3.9  MFR_SPECIFIC_08: ALERT_MASK (D8h)
        10. 8.5.3.10 MFR_SPECIFIC_09: DEVICE_SETUP (D9h)
        11. 8.5.3.11 MFR_SPECIFIC_10: BLOCK_READ (DAh)
        12. 8.5.3.12 MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh)
        13. 8.5.3.13 MFR_SPECIFIC_12: READ_AVG_VIN (DCh)
        14. 8.5.3.14 MFR_SPECIFIC_13: READ_AVG_VOUT (DDh)
        15. 8.5.3.15 MFR_SPECIFIC_14: READ_AVG_IIN (DEh)
        16. 8.5.3.16 MFR_SPECIFIC_14: READ_AVG_PIN (DFh)
        17. 8.5.3.17 MFR_SPECIFIC_15: READ_AVG_PIN
        18. 8.5.3.18 MFR_SPECIFIC_16: BLACK_BOX_READ (E0h)
        19. 8.5.3.19 MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h)
        20. 8.5.3.20 MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h)
      4. 8.5.4 Reading and Writing Telemetry Data and Warning Thresholds
      5. 8.5.5 Determining Telemetry Coefficients Empirically With Linear Fit
      6. 8.5.6 Writing Telemetry Data
      7. 8.5.7 PMBus Address Lines (ADR0, ADR1, ADR2)
      8. 8.5.8 SMBA Response
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 48-V, 10-A PMBus Hotswap Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design-In Procedure
          1. 9.2.1.2.1 Select RSNS and CL Setting
          2. 9.2.1.2.2 Selecting the Hotswap FETs
          3. 9.2.1.2.3 Select Power Limit
          4. 9.2.1.2.4 Set Fault Timer
          5. 9.2.1.2.5 Check MOSFET SOA
          6. 9.2.1.2.6 Set UVLO and OVLO Thresholds
            1. 9.2.1.2.6.1 Option A
            2. 9.2.1.2.6.2 Option B
            3. 9.2.1.2.6.3 Option C
            4. 9.2.1.2.6.4 Option D
          7. 9.2.1.2.7 Power Good Pin
          8. 9.2.1.2.8 Input and Output Protection
          9. 9.2.1.2.9 Final Schematic and Component Values
        3. 9.2.1.3 Application Curves
      2. 9.2.2 48-V, 20-A PMBus Hotswap Design
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1  Selecting the Sense Resistor and CL Setting
          2. 9.2.2.2.2  Selecting the Hotswap FETs
          3. 9.2.2.2.3  Select Power Limit
          4. 9.2.2.2.4  Set Fault Timer
          5. 9.2.2.2.5  Check MOSFET SOA
          6. 9.2.2.2.6  Switching to dv/dt-Based Start-Up
          7. 9.2.2.2.7  Choosing the VOUT Slew Rate
          8. 9.2.2.2.8  Select Power Limit and Fault Timer
          9. 9.2.2.2.9  Chose Input and Output Protection and Set Undervoltage, Overvoltage, and Power Good Thresholds
          10. 9.2.2.2.10 Final Schematic and Component Values
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

PWP Package
28-Pin
Top View
LM5066I 30115902.gif
Solder exposed pad to ground.

Pin Functions

PIN DESCRIPTION
NAME NO.
Exposed Pad Pad Exposed pad of TSSOP package
Solder to the ground plane to reduce thermal resistance
OUT 1 Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting and to monitor the output voltage.
GATE 2 Gate drive output
Connect to the external MOSFET's gate.
SENSE 3 Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS reaches overcurrent threshold the load current is limited and the fault timer activates.
VIN_K 4 Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN 5 Positive supply input
This pin is the input supply connection for the device.
N/C 6 No connection
UVLO/EN 7 Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. An internal 20-µA current source provides hysteresis. The enable threshold at the pin is nominally 2.48 V. This pin can also be used for remote shutdown control.
OVLO 8 Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin is 2.46 V.
AGND 9 Circuit ground
Analog device ground. Connect to GND at the pin.
GND 10 Circuit ground
SDAI 11 SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices.
SDAO 12 SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices.
SCL 13 SMBus clock
Clock pin for SMBus
SMBA 14 SMBus alert line
Alert pin for SMBus, active low
VREF 15 Internal reference
Internally generated precision reference used for analog-to-digital conversion. Connect a 1-µF capacitor on this pin to ground for bypassing.
DIODE 16 External diode
Connect this to a diode-configured MMBT3904 NPN transistor for temperature monitoring.
VAUX 17 Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full-scale input of 2.97 V.
ADR2 18 SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR1 19 SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR0 20 SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
VDD 21 Internal sub-regulator output
Internally sub-regulated 4.85-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing.
CL 22 Current limit range
Connect this pin to GND or leave floating to set the nominal over-current threshold at 50 mV. Connecting CL to VDD sets the overcurrent threshold to be 26 mV.
FB 23 Power Good feedback
An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at the pin is nominally 2.46 V. An internal 20-µA current source provides hysteresis.
RETRY 24 Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a fault.
TIMER 25 Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing.
PWR 26 Power limit set
An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum power dissipation allowed in the external series pass MOSFET.
N/C 27 No connection
PGD 28 Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above VFBTH (nominally 2.46 V) and the input supply is within its undervoltage and overvoltage thresholds. Connect to the output rail (external MOSFET source) or any other voltage to be monitored.