SNVSAJ3B March 2016 – February 2017 LM5165-Q1
The performance of any switching converter depends as much upon PCB layout as it does the component selection. The following guidelines are provided to assist with designing a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply's performance.
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize radiated EMI is to identify the pulsing current path and minimize the area of that path.
The critical switching loop of the power stage in terms of EMI is denoted in Figure 72. The topological architecture of a buck converter means that a particularly high di/dt current effective path exists in the loop comprising the input capacitor and the LM5165-Q1's integrated MOSFETs, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area.
The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's return terminal to the LM5165-Q1's GND pin and exposed PAD.
For the adjustable output voltage version of the LM5165-Q1, reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the input to the feedback comparator and, as such, is a high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path, the inductor and VIN path to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high feedback resistances, greater than 100 kΩ, are used to set the output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node and VIN path, such that there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This provides further shielding for the voltage feedback path from switching noise sources.
Figure 73 shows an example layout for the PCB top layer of a single-sided design. The bottom layer is essentially a full ground plane except for short connecting traces for SW, EN, and PGOOD.