SNVSAJ3B March   2016  – February 2017 LM5165-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integrated Power MOSFETs
      2. 7.3.2  Selectable PFM or COT Mode Converter Operation
      3. 7.3.3  COT Mode Light-Load Operation
      4. 7.3.4  Low Dropout Operation and 100% Duty Cycle Mode
      5. 7.3.5  Adjustable Output Voltage (FB)
      6. 7.3.6  Adjustable Current Limit
      7. 7.3.7  Precision Enable (EN) and Hysteresis (HYS)
      8. 7.3.8  Power Good (PGOOD)
      9. 7.3.9  Configurable Soft Start (SS)
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode in COT
      4. 7.4.4 Active Mode in PFM
      5. 7.4.5 Sleep Mode in PFM
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: Wide VIN, Low IQ COT Converter Rated at 5 V, 150 mA
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Switching Frequency - RT
          3. 8.2.1.2.3 Filter Inductor - LF
          4. 8.2.1.2.4 Output Capacitors - COUT
          5. 8.2.1.2.5 Series Ripple Resistor - RESR
          6. 8.2.1.2.6 Input Capacitor - CIN
          7. 8.2.1.2.7 Soft-Start Capacitor - CSS
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Small Solution Size PFM Converter Rated at 3.3 V, 50 mA
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Peak Current Limit Setting - RILIM
          2. 8.2.2.2.2 Switching Frequency - LF
          3. 8.2.2.2.3 Output Capacitor - COUT
          4. 8.2.2.2.4 Input Capacitor - CIN
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Design 3: High Density 12-V, 75-mA PFM Converter
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
          1. 8.2.3.2.1 Peak Current Limit Setting - RILIM
          2. 8.2.3.2.2 Switching Frequency - LF
          3. 8.2.3.2.3 Input and Output Capacitors - CIN, COUT
          4. 8.2.3.2.4 Feedback Resistors - RFB1, RFB2
          5. 8.2.3.2.5 Undervoltage Lockout Setpoint - RUV1, RUV2, RHYS
          6. 8.2.3.2.6 Soft Start - CSS
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Design 4: 3.3-V, 150-mA COT Converter With High Efficiency
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Application Curves
      5. 8.2.5 Design 5: 15-V, 150-mA, 600-kHz COT Converter
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
          1. 8.2.5.2.1 COT Output Ripple Voltage Reduction
        3. 8.2.5.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Compact PCB Layout for EMI Reduction
      2. 10.1.2 Feedback Resistor Layout
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
      3. 11.1.3 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

The performance of any switching converter depends as much upon PCB layout as it does the component selection. The following guidelines are provided to assist with designing a PCB with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.

Layout Guidelines

PCB layout is a critical for good power supply design. There are several paths that conduct high slew-rate currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade the power supply's performance.

  1. Bypass the VIN pin to GND with a low-ESR ceramic capacitor of X5R or X7R dielectric. Place CIN as close as possible to the LM5165-Q1 VIN and GND pins. Ground return paths for both the input and output capacitors should consist of localized top-side planes that connect to the GND pin and exposed PAD.
  2. Minimize the loop area formed by the input capacitor connections and the VIN and GND pins.
  3. Locate the power inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive capacitive coupling.
  4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
  5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
  6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-start, and enable components to the ground plane. This prevents any switched or load currents from flowing in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic output voltage ripple behavior.
  7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the input or output paths of the converter and maximizes efficiency.
  8. Minimize trace length to the FB pin. Locate both feedback resistors close to the FB pin. Place CFF (if used) directly in parallel with RFB1. Route the VOUT sense path away from noisy nodes and preferably on a layer at the other side of a shielding layer.
  9. Locate the components at RT and SS as close as possible to the device. Route with minimal trace lengths.
  10. Provide adequate heatsinking for the LM5165-Q1 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed PAD to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes.

Compact PCB Layout for EMI Reduction

Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to minimize radiated EMI is to identify the pulsing current path and minimize the area of that path.

The critical switching loop of the power stage in terms of EMI is denoted in Figure 72. The topological architecture of a buck converter means that a particularly high di/dt current effective path exists in the loop comprising the input capacitor and the LM5165-Q1's integrated MOSFETs, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing the effective loop area.

LM5165-Q1 Power_loops_nvsa47.gif Figure 72. Synchronous Buck Converter With Power Stage Critical Switching Loop

The input capacitor provides the primary path for the high di/dt components of the high-side MOSFET's current. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction. Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the capacitor's return terminal to the LM5165-Q1's GND pin and exposed PAD.

Feedback Resistor Layout

For the adjustable output voltage version of the LM5165-Q1, reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the input to the feedback comparator and, as such, is a high impedance node sensitive to noise. The output node is a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.

Route the voltage sense trace from the load to the feedback resistor divider away from the SW node path, the inductor and VIN path to avoid contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most important when high feedback resistances, greater than 100 kΩ, are used to set the output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node and VIN path, such that there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This provides further shielding for the voltage feedback path from switching noise sources.

Layout Example

Figure 73 shows an example layout for the PCB top layer of a single-sided design. The bottom layer is essentially a full ground plane except for short connecting traces for SW, EN, and PGOOD.

LM5165-Q1 Layout_diagram_nvsa47.gif Figure 73. PCB Layout Example