SNVSAH5A September   2017  – May 2020 LM73605 , LM73606

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Load Current VOUT = 5 V, fSW = 500 kHz, Auto Mode
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Synchronous Step-Down Regulator
      2. 7.3.2  Auto Mode and FPWM Mode
      3. 7.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 7.3.4  Adjustable Output Voltage
      5. 7.3.5  Enable and UVLO
      6. 7.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 7.3.7  Soft Start and Voltage Tracking
      8. 7.3.8  Adjustable Switching Frequency
      9. 7.3.9  Frequency Synchronization and Mode Setting
      10. 7.3.10 Internal Compensation and CFF
      11. 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 7.3.12 Power-Good and Overvoltage Protection
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 DCM Mode
        3. 7.4.3.3 PFM Mode
        4. 7.4.3.4 Fault Protection Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feedforward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS
        11. 8.2.2.11 Soft Start
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout For EMI Reduction
      2. 10.1.2 Ground Plane
      3. 10.1.3 Optimize Thermal Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.4 Adjustable Output Voltage

The voltage regulation loop in the LM73605 and LM73606regulate the FB pin voltage to be the same as the internal reference voltage. The output voltage of the LM73605 and LM73606 is set by a resistor divider to program the ratio from VOUT to VFB. The resistor divider is connected from the output to ground with the mid-point connecting to the FB pin.

LM73605 LM73606 output_volt_set_snvsah5.gifFigure 13. Output Voltage Setting by Resistor Divider

The internal voltage reference and feedback loop produce precise voltage regulation over temperature. TI recommends using divider resistors with 1% tolerance or better, and with temperature coefficient of 100 ppm or lower. Typically, RFBT = 10 kΩ to 100 kΩ is recommended. Larger RFBT and RFBB values reduce the quiescent current going through the divider, which help maintain high efficiency at very light load. Larger divider values also make the feedback path more susceptible to noise. If efficiency at very light load is critical in a certain application, RFBT up to 1 MΩ can be used.

RFBB can be calculated by Equation 7:

Equation 7. LM73605 LM73606 eq_RFBB_snvsah5.gif

The minimum programmable VOUT equals VFB, with RFBB open. The maximum VOUT is limited by the maximum duty cycle at a given frequency:

Equation 8. DMAX = 1 – (tOFF-MIN / TSW)

where

  • tOFF-MIN is the minimum off time of the HS switch
  • TSW = 1 / fSW is the switching period

Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX.

Power losses in the circuit reduces the maximum output voltage. The LM73605 and LM73606fold back switching frequency under tOFF_MIN condition to further extend VOUT_MAX. The device maintains output regulation with lower input voltage. The minimum foldback frequency is limited by the maximum HS on-time, tON_MAX. Maximum output voltage with frequency foldback can be estimated by:

Equation 9. LM73605 LM73606 eq_maximum_outputvoltage_Tonmax_snvsah5.gif

The voltage drops on the HS MOSFET and inductor DCR have been taken into account in Equation 9. The switching losses were not included.

If the resistor divider is not connected properly, the output voltage cannot be regulated because the feedback loop cannot obtain correct output voltage information. If the FB pin is shorted to ground or disconnected, the output voltage is driven close to VIN. The load connected to the output can be damaged under this condition. Do not short FB to ground or leave it open circuit during operation.

The FB pin is a noise sensitive node. It is important to place the resistor divider as close as possible to the FB pin, and route the feedback node with a short and thin trace. The trace connecting VOUT to RFBT can be long, but it must be routed away from the noisy area of the PCB. For more layout recommendations, see the Layout section.