SNLS247H April   2007  – June 2016 LMH0302

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC
    6. 6.6 Electrical Characteristics - AC
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Interfacing
      2. 7.3.2 Output Interfacing
      3. 7.3.3 Output Slew Rate Control
      4. 7.3.4 Output Enable
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for All Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

TI recommends the following layout guidelines for the LMH0302:

  1. The RREF 1% tolerance resistor must be placed as close as possible to the RREF pin. In addition, the copper in the plane layers below the RREF network must be removed to minimize parasitic capacitance.
  2. Choose a suitable board stackup that supports 75-Ω single-ended trace and 100-Ω differential trace routing on the top layer of the board. This is typically done with a Layer 2 ground plane reference for the 100-Ω differential traces and a second ground plane at Layer 3 reference for the 75-Ω single-ended traces.
  3. Use single-ended uncoupled trace designed with 75-Ω impedance for signal routing to SDO and SDO. The trace width is typically 8-10 mil reference to a ground plane at Layer 3.
  4. Use coupled differential traces with 100-Ω impedance for signal routing to SDI and SDI. They are usually
    5-mil to 8-mil trace width reference to a ground plane at Layer 2.
  5. Place anti-pad (ground relief) on the power and ground planes directly under the 4.7-μF AC-coupling capacitor, return loss network, and IC landing pads to minimize parasitic capacitance. The size of the anti-pad depends on the board stackup and can be determined by a 3-dimension electromagnetic simulation tool.
  6. Use a well-designed BNC footprint to ensure the BNC’s signal landing pad achieves 75-Ω characteristic impedance. BNC suppliers usually provide recommendations on BNC footprint for best results.
  7. Keep trace length short between the BNC and SDO. The trace routing for SDO and SDO must be symmetrical, approximately equal lengths, and equal loading.
  8. The exposed pad EP of the package must be connected to the ground plane through an array of vias. These vias are solder-masked to avoid solder flow into the plated-through holes during the board manufacturing process.
  9. Connect each supply pin (VCC and VEE) to the power or ground planes with a short via. The via is usually placed tangent to the landing pads of the supply pins with the shortest trace possible.
  10. Power-supply bypass capacitors must be placed close to the supply pins.

10.2 Layout Example

Figure 6 shows an example of proper layout requirements for the LMH0302.

LMH0302 lmh0303_layout_example.gif Figure 6. LMH0302 High-Speed Traces Layout Example