SNAS522K September 2011 – December 2023 LMK03806
PRODUCTION DATA
The frequency of the PLL reference input to the PLL Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency.
R29[26:24] | OSCin FREQUENCY |
---|---|
0 (0x00) | 0 to 63 MHz |
1 (0x01) | >63 MHz to 127 MHz |
2 (0x02) | >127 MHz to 255 MHz |
3 (0x03) | Reserved |
4 (0x04) | >255 MHz to 500 MHz |