SNAS703 Data sheet

SNAS703 April 2017 LMK04828-EP

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

NKD|64
- MPQS032B

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽²⁾

		MIN	MAX	UNIT
V_CC	Supply voltage ⁽¹⁾	–0.3	3.6	V
V_IN	Input voltage	–0.3	(V_CC + 0.3)	V
T_L	Lead temperature (solder 4 seconds)		260	°C
T_J	Junction temperature		150	°C
I_IN	Differential input current (CLKinX/X, OSCin/OSCin, FBCLKin/FBCLKin, Fin/Fin)		±5	mA
MSL	Moisture sensitivity level		3
T_stg	Storage temperature	–65	150	°C

(1) Never to exceed 3.6 V.

(2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250
		Machine Model (MM)	±150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
T_J	Junction temperature			125	°C
T_A	Ambient temperature	–55	25	105	°C
V_CC	Supply voltage	3.15	3.3	3.45	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMK04828-EP	UNIT
		NKD (WQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	24.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽³⁾	6.1	°C/W
R_θJB	Junction-to-board thermal resistance⁽⁴⁾	3.5	°C/W
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	3.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁷⁾	0.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, Ψ_JB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

(3.15 V < V_CC < 3.45 V, –55 °C < T_A < +105°C. Typical values at V_CC = 3.3 V, T_A = 25 °C, at the recommended operating conditions and are not assured.)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{CC_PD}	Power-down supply current				1	3	mA
I_{CC_CLKS}	Supply current⁽²⁾	14 HSDS 8 mA clocks enabled PLL1 and PLL2 locked.			565	670	mA
CLKin0/0, CLKin1/1, and CLKin2/2* INPUT CLOCK SPECIFICATIONS
f_CLKin	Clock input frequency			0.001		750	MHz
SLEW_CLKin	Clock input slew rate ⁽³⁾	20% to 80%		0.15	0.5		V/ns
V_IDCLKin	Differential clock input voltage⁽¹⁾ See Figure 4	AC-coupled		0.125		1.55	\|V\|
V_SSCLKin	Differential clock input voltage⁽¹⁾ See Figure 4	AC-coupled		0.25		3.1	Vpp
V_CLKin	Clock input Single-ended input voltage	AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 0 (Bipolar)		0.25		2.4	Vpp
V_CLKin	Clock input Single-ended input voltage	AC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS)		0.35		2.4	Vpp
\|V_{CLKinX-offset}\|	DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX)	Each pin is AC-coupled, CLKin0/1/2 CLKinX_TYPE = 0 (Bipolar)			0		\|mV\|
	DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX)	Each pin is AC-coupled, CLKin0/1 CLKinX_TYPE = 1 (MOS)			55		\|mV\|
	DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2)	Each pin is AC-coupled CLKinX_TYPE = 1 (MOS)			20		\|mV\|
V_CLKin- V_IH	High input voltage	DC-coupled to CLKinX; CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS)		2		V_CC	V
V_CLKin– V_IL	Low input voltage			0		0.4	V
FBCLKin/FBCLKin* and Fin/Fin* INPUT SPECIFICATIONS
f_FBCLKin	Clock input frequency for 0-delay with external feedback.	AC-coupled CLKinX_TYPE = 0 (Bipolar)		0.001		750	MHz
f_Fin	Clock input frequency for external VCO mode	AC-coupled ⁽⁴⁾ CLKinX_TYPE = 0 (Bipolar)		0.001		3100	MHz
f_Fin	Clock input frequency for distribution mode	AC-coupled CLKinX_TYPE = 0 (Bipolar)		0.001		3200	MHz
V_FBCLKin/Fin	Single-ended clock input voltage	AC-coupled CLKinX_TYPE = 0 (Bipolar)		0.25		2	Vpp
SLEW_FBCLKin/Fin	Slew rate on CLKin ⁽³⁾	AC-coupled; 20% to 80%; (CLKinX_TYPE = 0)		0.15	0.5		V/ns
PLL1 SPECIFICATIONS
f_PD1	PLL1 phase detector frequency					40	MHz
I_CPout1SOURCE	PLL1 charge pump source current ⁽⁵⁾	V_CPout1 = V_CC/2, PLL1_CP_GAIN = 0			50		µA
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 1			150
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 2			250
		…			…
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 14			1450
		V_CPout1 = V_CC/2, PLL1_CP_GAIN = 15			1550
I_CPout1SINK	PLL1 Charge pump sink current ⁽⁵⁾	V_CPout1=V_CC/2, PLL1_CP_GAIN = 0			–50		µA
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 1			–150
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 2			–250
		…			…
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 14			–1450
		V_CPout1=V_CC/2, PLL1_CP_GAIN = 15			–1550
I_CPout1%MIS	Charge pump sink / source mismatch	V_CPout1 = V_CC/2, T = 25 °C			1%	10%
I_CPout1V_TUNE	Magnitude of charge pump current variation vs. charge pump voltage	0.5 V < V_CPout1 < V_CC - 0.5 V T_A = 25 °C			4%
I_CPout1%TEMP	Charge pump current vs. temperature variation				4%
I_CPout1TRI	Charge pump TRI-STATE leakage current	0.5 V < V_CPout < V_CC - 0.5 V				10	nA
PN10kHz	PLL 1/f Noise at 10-kHz offset. Normalized to 1-GHz Output Frequency	PLL1_CP_GAIN = 350 µA			–117		dBc/Hz
PN10kHz		PLL1_CP_GAIN = 1550 µA			–118		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 350 µA			–221.5		dBc/Hz
PN1Hz	Normalized phase noise contribution	PLL1_CP_GAIN = 1550 µA			–223		dBc/Hz
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
f_OSCin	PLL2 reference input ⁽⁷⁾					500	MHz
SLEW_OSCin	PLL2 reference clock minimum slew rate on OSCin ⁽³⁾	20% to 80%		0.15	0.5		V/ns
V_OSCin	Input voltage for OSCin or OSCin*	AC-coupled; Single-ended (Unused pin AC-coupled to GND)		0.2		2.4	Vpp
V_IDOSCin	Differential voltage swing See Figure 4	AC-coupled		0.2		1.55	\|V\|
V_SSOSCin	Differential voltage swing See Figure 4	AC-coupled		0.4		3.1	Vpp
\|V_OSCin-offset\|	DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX)	Each pin is AC-coupled			20		\|mV\|
f_{doubler_max}	Doubler input frequency ⁽⁶⁾	EN_PLL2_REF_2X = 1⁽⁸⁾; OSCin Duty Cycle 40% to 60%				155	MHz
CRYSTAL OSCILLATOR MODE SPECIFICATIONS
F_XTAL	Crystal frequency range	Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz)		10		40	MHz
C_IN	Input capacitance of OSCin port	–40 to 85 °C			1		pF
PLL2 PHASE DETECTOR and CHARGE PUMP SPECIFICATIONS
f_PD2	Phase detector frequency ⁽⁶⁾					155	MHz
I_CPoutSOURCE	PLL2 charge pump source current ⁽⁵⁾	V_CPout2 = V_CC/2, PLL2_CP_GAIN = 0			100		µA
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 1			400
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 2			1600
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 3			3200
I_CPoutSINK	PLL2 charge pump sink current ⁽⁵⁾	V_CPout2 = V_CC/2, PLL2_CP_GAIN = 0			–100		µA
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 1			–400
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 2			–1600
		V_CPout2 = V_CC/2, PLL2_CP_GAIN = 3			–3200
I_CPout2%MIS	Charge pump sink/source mismatch	V_CPout2 = V_CC/2, T_A = 25°C			1%	10%
I_CPout2V_TUNE	Magnitude of charge pump current vs. charge pump voltage variation	0.5 V < V_CPout2 < V_CC – 0.5 V			4%
I_CPout2%TEMP	Charge pump current vs. temperature variation				4%
I_CPout2TRI	Charge pump leakage	0.5 V < V_CPout2 < V_CC – 0.5 V				20	nA
PN10kHz	PLL 1/f noise at 10-kHz offset⁽⁹⁾. Normalized to 1-GHz output frequency	PLL2_CP_GAIN = 400 µA			–118		dBc/Hz
PN10kHz		PLL2_CP_GAIN = 3200 µA			–121		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽¹⁰⁾	PLL2_CP_GAIN = 400 µA			–222.5		dBc/Hz
PN1Hz	Normalized phase noise contribution⁽¹⁰⁾	PLL2_CP_GAIN = 3200 µA			–227		dBc/Hz
INTERNAL VCO SPECIFICATIONS
f_VCO	LMK04828-EP VCO tuning range	VCO0		2450		2755	MHz
f_VCO	LMK04828-EP VCO tuning range	VCO1		2875		3080	MHz
K_VCO	LMK04828-EP fine tuning sensitivity	VCO0	Lower end		17		MHz/V
		VCO0	Higher end		27
		VCO1	Lower end		17
		VCO1	Higher end		23
\|ΔT_CL\|	Allowable temperature drift for continuous lock⁽¹¹⁾	After programming for lock, no changes to output configuration are permitted to assure continuous lock.				160	°C
NOISE FLOOR
L(f)_CLKout	LMK04828-EP, VCO0, noise floor 20-MHz offset ⁽¹⁸⁾	245.76 MHz	LVDS		–156.3		dBc/Hz
			HSDS 6 mA		–158.4
			HSDS 8 mA		–159.3
			HSDS 10 mA		–158.9
			LVPECL16 with 240 Ω		–161.6
			LVPECL20 with 240 Ω		–162.5
			LCPECL		–162.1
L(f)_CLKout	LMK04828-EP, VCO1, noise floor 20-MHz offset ⁽¹⁸⁾	245.76 MHz	LVDS		–155.7		dBc/Hz
			HSDS 6 mA		–157.5
			HSDS 8 mA		–158.1
			HSDS 10 mA		–157.7
			LVPECL16 with 240 Ω		–160.3
			LVPECL20 with 240 Ω		–161.1
			LCPECL		–160.8
CLKout CLOSED LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹²⁾
L(f)_CLKout	LMK04828-EP VCO0 SSB phase noise ⁽¹⁸⁾ 245.76 MHz	Offset = 1 kHz			–124.3		dBc/Hz
		Offset = 10 kHz			–134.7
		Offset = 100 kHz			–136.5
		Offset = 1 MHz			–148.4
		Offset = 10 MHz	LVDS		–156.4
			HSDS 8 mA		–159.1
			LVPECL16 with 240 Ω		–160.8
L(f)_CLKout	LMK04828-EP VCO1 SSB phase noise ⁽¹⁸⁾ 245.76 MHz	Offset = 1 kHz			–124.2		dBc/Hz
		Offset = 10 kHz			–134.4
		Offset = 100 kHz			–135.2
		Offset = 1 MHz			–151.5
		Offset = 10 MHz	LVDS		–159.9
			HSDS 8 mA		–155.8
			LVPECL16 with 240 Ω		–158.1
CLKout CLOSED LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO⁽¹²⁾
J_CLKout	LMK04828-EP, VCO0 f_CLKout = 245.76 MHz Integrated RMS jitter ⁽¹⁸⁾	LVDS, BW = 100 Hz to 20 MHz			112		fs rms
		LVDS, BW = 12 kHz to 20 MHz			109
		HSDS 8 mA, BW = 100 Hz to 20 MHz			102
		HSDS 8 mA, BW = 12 kHz to 20 MHz			99
		LVPECL16 with 240 Ω, BW = 100 Hz to 20 MHz			98
		LVPECL20 with 240 Ω, BW = 12 kHz to 20 MHz			95
		LCPECL with 240 Ω, BW = 100 Hz to 20 MHz			96
		LCPECL with 240 Ω, BW = 12 kHz to 20 MHz			93
	LMK04828-EP, VCO1 f_CLKout = 245.76 MHz Integrated RMS jitter ⁽¹⁸⁾	LVDS, BW = 100 Hz to 20 MHz			108		fs rms
		LVDS, BW = 12 kHz to 20 MHz			105
		HSDS 8 mA, BW = 100 Hz to 20 MHz			98
		HSDS 8 mA, BW = 12 kHz to 20 MHz			94
		LVPECL16 with 240 Ω, BW = 100 Hz to 20 MHz			93
		LVPECL20 with 240 Ω, BW = 12 kHz to 20 MHz			90
		LCPECL with 240 Ω, BW = 100 Hz to 20 MHz			91
		LCPECL with 240 Ω, BW = 12 kHz to 20 MHz			88
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY
f_{CLKout-start-up}	Default output clock frequency at device power on ⁽¹³⁾	LMK04828-EP			315		MHz
f_OSCout	OSCout frequency	See ⁽⁶⁾				500	MHz
CLOCK SKEW AND DELAY
\|T_SKEW\|	DCLKoutX to SDCLKoutY F_CLK = 245.76 MHz, R_L= 100 Ω AC-coupled ⁽¹⁴⁾	Same pair, same format⁽¹⁵⁾ SDCLKoutY_MUX = 0 (device clock)				25	\|ps\|
\|T_SKEW\|	Maximum DCLKoutX or SDCLKoutY to DCLKoutX or SDCLKoutY F_CLK = 245.76 MHz, R_L= 100 Ω AC-coupled	Any pair, same format ⁽¹⁵⁾ SDCLKoutY_MUX = 0 (device clock)			50		\|ps\|
ts_JESD204B	SYSREF to device clock setup time base reference. See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required.	SDCLKoutY_MUX = 1 (SYSREF) SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div + DCC + HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 SDCLKoutY_HS = 0			–80		ps
t_PDCLKin0_ SDCLKout1	Propagation delay from CLKin0 to SDCLKout1	CLKin0_OUT_MUX = 0 (SYSREF Mux) SYSREF_CLKin0_MUX = 1 (CLKin0) SDCLKout1_PD = 0 SDCLKout1_DDLY = 0 (Bypass) SDCLKout1_MUX = 1 (SR) EN_SYNC = 1 LVPECL16 with 240 Ω			0.65		ns
f_ADLYmax	Maximum analog delay frequency	DCLKoutX_MUX = 4			1536		MHz
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout)
V_OD	Differential output voltage	T = 25°C, DC measurement AC-coupled to receiver input R_L = 100-Ω differential termination			395		\|mV\|
ΔV_OD	Change in magnitude of V_OD for complementary output states			–60		60	mV
V_OS	Output offset voltage			1.125	1.25	1.375	V
ΔV_OS	Change in V_OS for complementary output states					35	\|mV\|
T_R / T_F	Output rise time	20% to 80%, R_L = 100 Ω, 245.76 MHz			180		ps
T_R / T_F	Output fall time	80% to 20%, R_L = 100 Ω			180		ps
I_SA I_SB	Output short-circuit current - single-ended	Single-ended output shorted to GND T = 25 °C		–24		24	mA
I_SAB	Output short-circuit current - differential	Complimentary outputs tied together		–12		12	mA
6-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH		T = 25 °C, DC measurement Termination = 50 Ω to V_CC – 1.42 V			V_CC – 1.05
V_OL					V_CC – 1.64
V_OD	Differential output voltage				590		\|mV\|
ΔV_OD	Change in V_OD for complementary output states			–80		80	mVpp
8-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
T_R / T _F	Output rise time	245.76 MHz, 20% to 80%, R_L = 100 Ω			170		ps
T_R / T _F	Output fall time	245.76 MHz, 80% to 20%, R_L = 100 Ω			170		ps
V_OH		DC measurement Termination = 50 Ω to V_CC – 1.64 V			V_CC – 1.26
V_OL					V_CC – 2.06
V_OD	Differential output voltage				800		\|mV\|
ΔV_OD	Change in V_OD for complementary output states			–115		115	mVpp
10-mA HSDS CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH		T = 25 °C, DC measurement Termination = 50 Ω to V_CC – 1.43 V			V_CC – 0.99
V_OL					V_CC – 1.97
V_OD					980		mVpp
ΔV_OD	Change in V_OD for complementary output states			–115		115	mVpp
LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
T_R / T_F	20% to 80% output rise	R_L = 100 Ω, emitter resistors = 240 Ω to GND DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp)			150		ps
T_R / T_F	80% to 20% output fall time				150		ps
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH	Output high voltage	DC Measurement Termination = 50 Ω to V_CC – 2 V			V_CC – 1.04		V
V_OL	Output low voltage				V_CC – 1.80		V
V_OD	Output voltage See Figure 5				760		\|mV\|
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH	Output high voltage	DC Measurement Termination = 50 Ω to V_CC – 2.3 V			V_CC – 1.09		V
V_OL	Output low voltage				V_CC – 2.05		V
V_OD	Output voltage See Figure 5				960		\|mV\|
LCPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY)
V_OH	Output high voltage	DC Measurement Termination = 50 Ω to 0.5 V			1.57		V
V_OL	Output low voltage				0.62		V
V_OD	Output voltage See Figure 5				950		\|mV\|
LVCMOS CLOCK OUTPUTS (OSCout)
f_CLKout	Maximum frequency See ⁽¹⁶⁾	5-pF Load		250			MHz
V_OH	Output high voltage	1-mA Load		V_CC – 0.1			V
V_OL	Output low voltage	1-mA Load				0.1	V
I_OH	Output high current (source)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
I_OL	Output low current (sink)	V_CC = 3.3 V, V_O = 1.65 V			28		mA
DUTY_CLK	Output duty cycle⁽¹⁷⁾	V_CC/2 to V_CC/2, F_CLK = 100 MHz, T = 25°C			50%
T_R	Output rise time	20% to 80%, R_L = 50 Ω, C_L = 5 pF			400		ps
T_F	Output fall time	80% to 20%, R_L = 50 Ω, C_L = 5 pF			400		ps
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO)
V_OH	High-level output voltage	I_OH = –500 µA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4		V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6				0.4	V
DIGITAL OUTPUT (SDIO)
V_OH	High-level output voltage	I_OH = –500 µA ; during SPI read. SDIO_RDBK_TYPE = 0		V_CC – 0.4			V
V_OL	Low-level output voltage	I_OL = 500 µA ; during SPI read. SDIO_RDBK_TYPE = 0 or 1				0.4	V
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*)
V_IH	High-level input voltage			1.2		V_CC	V
V_IL	Low-level input voltage					0.4	V
DIGITAL INPUTS (CLKinX_SEL)
I_IH	High-level input current V_IH = V_CC	CLKin_SELX_TYPE = 0, (high impedance)		–5		5	µA
		CLKin_SELX_TYPE = 1 (pullup)		–5		5
		CLKin_SELX_TYPE = 2 (pulldown)		10		80
I_IL	Low-level input current V_IL = 0 V	CLKin_SELX_TYPE = 0, (high impedance)		–5		5	µA
		CLKin_SELX_TYPE = 1 (pullup)		–40		–5
		CLKin_SELX_TYPE = 2 (pulldown)		–5		5
DIGITAL INPUT (RESET/GPO)
I_IH	High-level input current V_IH = V_CC	RESET_TYPE = 2 (pulldown)		10		80	µA
I_IL	Low-level input current V_IL = 0 V	RESET_TYPE = 0 (high impedance)		–5		5	µA
		RESET_TYPE = 1 (pullup)		–40		–5
		RESET_TYPE = 2 (pulldown)		–5		5
DIGITAL INPUTS (SYNC)
I_IH	High-level input current	V_IH = V_CC				25	µA
I_IL	Low-level input current	V_IL = 0 V		–5		5	µA
DIGITAL INPUTS (SCK, SDIO, CS*)
I_IH	High-level input current	V_IH = V_CC		–5		5	µA
I_IL	Low-level input current	V_IL = 0		–5		5	µA
DIGITAL INPUT TIMING
t_HIGH		RESET pin held high for device reset		25			ns

(1) See Differential Voltage Measurement Terminology for definition of V_ID and V_OD voltages.

(2) See the applications section of Power Supply Recommendations for I_CC for specific part configuration and how to calculate I_CC for a specific design.

(3) To meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device functions at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.

(4) Assured by characterization.

(5) This parameter is programmable.

(6) Assured by characterization. ATE tested at 122.88 MHz.

(7) F_OSCin maximum frequency assured by characterization. Production tested at 122.88 MHz.

(8) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.

(9) A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L_{PLL_flicker}(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10-kHz offset and a 1-GHz carrier frequency. PN10kHz = L_{PLL_flicker}(10 kHz) – 20log(F_out / 1 GHz), where L_{PLL_flicker}(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L_{PLL_flicker}(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L_{PLL_flicker}(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}(f).

(10) A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L_{PLL_flat}(f), is defined as: PN1HZ=L_{PLL_flat}(f) - 20log(N) – 10log(f_PDX). L_{PLL_flat}(f) is the single side band phase noise measured at an offset frequency, f, in a 1-Hz bandwidth and f_PDX is the phase detector frequency of the synthesizer. L_{PLL_flat}(f) contributes to the total noise, L(f).

(11) Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of –55°C to 105°C without violating specifications.

(12) VCXO used is a 122.88-MHz Crystek CVHD-950-122.880.

(13) OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port.

(14) Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode.

(15) LVPECL uses a 120-Ω emitter resistor, LVDS and HSDS use a 560-Ω shunt.

(16) Assured by characterization. ATE tested to 10 MHz.

(17) Assumes OSCin has 50% input duty cycle.

(18) Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0.

(19) 20 MHz

7.6 SPI Interface Timing

			MIN	MAX	UNIT
td_s	Setup time for SDI edge to SCLK rising edge	See Figure 1	10		ns
td_H	Hold time for SDI edge from SCLK rising edge	See Figure 1	10		ns
t_SCLK	Period of SCLK	See Figure 1	50⁽¹⁹⁾		ns
t_HIGH	High width of SCLK	See Figure 1	25		ns
t_LOW	Low width of SCLK	See Figure 1	25		ns
tc_s	Setup time for CS* falling edge to SCLK rising edge	See Figure 1	10		ns
tc_H	Hold time for CS* rising edge from SCLK rising edge	See Figure 1	30		ns
td_v	SCLK falling edge to valid read back data	See Figure 1		20	ns

7.7 Timing Diagram

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming.

4-wire mode read back has the same timing as the SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

W1 and W0 is written as 0.

Figure 1. SPI Timing Diagram

7.8 Typical Characteristics – Clock Output AC Characteristics

NOTE: These plots show performance at frequencies beyond the point at which the part is ensured to operate in order to give an idea of the capabilities of the part. They do not imply any sort of ensured specification.
For Figure 2 and Figure 3, CLKout2_3_IDL=1; CLKout2_3_ODL=0; LVPECL20 with 240-Ω emitter resistors; DCLKout2 Frequency = 245.76 MHz; DCLKout2_MUX = 0 (Divider). Balun is ADT2-1T+.

LMK04828-EP tc_lmk04828b_automate_data,LMK04828b-1013-27,245.76 MHz, CLKout2 LVPECL20, Div10, MuxDivider, IDL1, ODL0_pndata_CLKout2_ADT21T_VCO0.png

VCO_MUX = 0 (VCO0)	PLL2 Loop Filter Bandwidth = 344 kHz
VCO0 = 2457.6 MHz	PLL2 Phase Margin = 73°
DCLKout2_DIV = 10

Figure 2. LMK04828-EP DCLKout2 Phase Noise

LMK04828-EP tc_lmk04828b_automate_data,LMK04828b-1013-27,245.76 MHz, CLKout2 LVPECL20, Div12, MuxDivider, IDL1, ODL0_pndata_CLKout2_ADT21T_VCO1.png

VCO_MUX = 1 (VCO1)	PLL2 Loop Filter Bandwidth = 233 kHz
VCO = 2949.12 MHz	PLL2 Phase Margin = 70°
DCLKout2_DIV = 12

Figure 3. LMK04828-EP DCLKout2 Phase Noise