SNAS859 March   2024 LMK05318B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Device Start-Up Modes
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: 4-Layer JEDEC Standard PCB
    5. 5.5 Thermal Information: 10-Layer Custom PCB
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 7.2 Functional Block Diagram
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 DPLL Mode
      3. 7.2.3 APLL-Only Mode
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO_P/N)
      2. 7.3.2  Reference Inputs (PRIREF_P/N and SECREF_P/N)
      3. 7.3.3  Clock Input Interfacing and Termination
      4. 7.3.4  Reference Input Mux Selection
        1. 7.3.4.1 Automatic Input Selection
        2. 7.3.4.2 Manual Input Selection
      5. 7.3.5  Hitless Switching
        1. 7.3.5.1 Hitless Switching With 1-PPS Inputs
      6. 7.3.6  Gapped Clock Support on Reference Inputs
      7. 7.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.7.1 XO Input Monitoring
        2. 7.3.7.2 Reference Input Monitoring
          1. 7.3.7.2.1 Reference Validation Timer
          2. 7.3.7.2.2 Amplitude Monitor
          3. 7.3.7.2.3 Frequency Monitoring
          4. 7.3.7.2.4 Missing Pulse Monitor (Late Detect)
          5. 7.3.7.2.5 Runt Pulse Monitor (Early Detect)
          6. 7.3.7.2.6 Phase Valid Monitor for 1-PPS Inputs
        3. 7.3.7.3 PLL Lock Detectors
        4. 7.3.7.4 Tuning Word History
        5. 7.3.7.5 Status Outputs
        6. 7.3.7.6 Interrupt
      8. 7.3.8  PLL Relationships
        1. 7.3.8.1  PLL Frequency Relationships
        2. 7.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 7.3.8.3  APLL Reference Paths
          1. 7.3.8.3.1 APLL XO Doubler
          2. 7.3.8.3.2 APLL1 XO Reference (R) Divider
          3. 7.3.8.3.3 APLL2 Reference (R) Dividers
        4. 7.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.8.5  APLL Feedback Divider Paths
          1. 7.3.8.5.1 APLL1 N Divider With SDM
          2. 7.3.8.5.2 APLL2 N Divider With SDM
        6. 7.3.8.6  APLL Loop Filters (LF1, LF2)
        7. 7.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2)
          1. 7.3.8.7.1 VCO Calibration
        8. 7.3.8.8  APLL VCO Clock Distribution Paths (P1, P2)
        9. 7.3.8.9  DPLL Reference (R) Divider Paths
        10. 7.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 7.3.8.11 DPLL Loop Filter (DLF)
        12. 7.3.8.12 DPLL Feedback (FB) Divider Path
      9. 7.3.9  Output Clock Distribution
      10. 7.3.10 Output Channel Muxes
      11. 7.3.11 Output Dividers (OD)
      12. 7.3.12 Clock Outputs (OUTx_P/N)
        1. 7.3.12.1 AC-Differential Output (AC-DIFF)
        2. 7.3.12.2 HCSL Output
        3. 7.3.12.3 1.8V LVCMOS Output
        4. 7.3.12.4 Output Auto-Mute During LOL
      13. 7.3.13 Glitchless Output Clock Start-Up
      14. 7.3.14 Clock Output Interfacing and Termination
      15. 7.3.15 Output Synchronization (SYNC)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up Modes
        1. 7.4.1.1 EEPROM Mode
      2. 7.4.2 PLL Operating Modes
        1. 7.4.2.1 Free-Run Mode
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 Locked Mode
        4. 7.4.2.4 Holdover Mode
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 7.4.4.1 DCO Frequency Step Size
        2. 7.4.4.2 DCO Direct-Write Mode
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Communication
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Communication
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map and EEPROM Map Generation
      5. 7.5.5 General Register Programming Sequence
      6. 7.5.6 EEPROM Programming Flow
        1. 7.5.6.1 EEPROM Programming Using Method #1 (Register Commit)
          1. 7.5.6.1.1 Write SRAM Using Register Commit
          2. 7.5.6.1.2 Program EEPROM
        2. 7.5.6.2 EEPROM Programming Using Method #2 (Direct Writes)
          1. 7.5.6.2.1 Write SRAM Using Direct Writes
          2. 7.5.6.2.2 User-Programmable Fields In EEPROM
      7. 7.5.7 Read SRAM
      8. 7.5.8 Read EEPROM
      9. 7.5.9 EEPROM Start-Up Mode Default Configuration
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PDN) Pin
      3. 8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.3.1 Mixing Supplies
        2. 8.1.3.2 Power-On Reset (POR) Circuit
        3. 8.1.3.3 Powering Up From a Single-Supply Rail
        4. 8.1.3.4 Power Up From Split-Supply Rails
        5. 8.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 8.1.4 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
      2. 8.4.2 Device Current and Power Consumption
        1. 8.4.2.1 Current Consumption Calculations
        2. 8.4.2.2 Power Consumption Calculations
        3. 8.4.2.3 Example
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
        1. 8.5.3.1 Support for PCB Temperature up to 105°C
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Reference Inputs (PRIREF_P/N and SECREF_P/N)

The reference inputs (PRIREF and SECREF) can accept differential or single-ended clocks. Each input has programmable input type, termination, and AC-coupled input biasing configurations as shown in Figure 7-7. Each input buffer drives the reference input mux of the DPLL block. The DPLL input mux can select from any of the reference inputs. The DPLL can switch between inputs with different frequencies if the inputs can be divided-down to a common frequency by DPLL R dividers. The reference input paths also drive the various detector blocks for reference input monitoring and validation.

GUID-C2E3F836-8EC4-4656-B7E6-94A91E222FD4-low.gifFigure 7-7 Reference Input Buffer

Table 7-2 lists the reference input buffer configurations for common clock interface types.

Table 7-2 Reference Input Buffer Modes
xxxREF_TYPE (R46[3:0] / R46[7:4])xxxREF_DC_
MODE
(R40[2] / (R40[3])		INPUT TYPEINTERNAL SWITCH SETTINGS
INTERNAL TERM.
(S1, S2)(1)		LVCMOS SLEW RATE DETECT (S4)(2)LVCMOS INTERNAL AC CAPACITOR BYPASS MODE (S5)(3)
0x000x00Differential
(externally DC- or AC-coupled, internally AC-coupled)		OFFOFFOFF

0x03

0x00Differential
(externally DC- or AC-coupled, internally terminated with 100Ω and AC-coupled)		100ΩOFFOFF
0x040x00HCSL
(externally DC-coupled, internally terminated with 50Ω and AC-coupled)		50ΩOFFOFF

0x08

0x00LVCMOS
(externally DC-coupled, internally AC-coupled)		OFFONOFF

0x08

0x01LVCMOS
(externally DC-coupled, internally DC-coupled)		OFFOFFON

0x0C

0x00Single-ended
(externally DC-coupled, internally terminated with 50Ω and AC-coupled)		50ΩONOFF
(1) S1, S2: OFF = External termination is assumed.
(2) S4: OFF = Differential input amplitude detector is used for all input types except LVCMOS or Single-ended.
(3) S5: OFF = Internal AC Coupling capacitor (7pF) is used. Switch S5 is set by REF_DC_MODE register. R40[3] can be used to set S5 for Primary Reference. R40[2] can be used to set S5 for Secondary Reference.