SNOSB31J July   2009  – December 2014 LMX2541

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Not Ensured Characteristics
      2. 7.7.2 Output Power in Bypass Mode
      3. 7.7.3 Output Power in Divided Mode
      4. 7.7.4 RFout Output Impedance
        1. 7.7.4.1 OSCin and Fin Sensitivity
  8. Parameter Measurement Information
    1. 8.1 Bench Test Setups
      1. 8.1.1 Charge Pump Current Measurements
      2. 8.1.2 Charge Pump Current Definitions
        1. 8.1.2.1 Charge Pump Current Definitions
        2. 8.1.2.2 Variation of Charge Pump Current Magnitude vs. Charge Pump Voltage
        3. 8.1.2.3 Variation of Charge Pump Current Magnitude vs. Temperature
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  PLL Reference Oscillator Input Pins
      2. 9.3.2  PLL R Divider
      3. 9.3.3  PLL Phase Detector and Charge Pump
      4. 9.3.4  PLL N Divider and Fractional Circuitry
      5. 9.3.5  Partially Integrated Loop Filter
      6. 9.3.6  Low Noise, Fully Integrated VCO
      7. 9.3.7  Programmable VCO Divider
      8. 9.3.8  Programmable RF Output Buffer
      9. 9.3.9  Powerdown Modes
      10. 9.3.10 Fastlock
      11. 9.3.11 Lock Detect
      12. 9.3.12 Current Consumption
      13. 9.3.13 Fractional Spurs
        1. 9.3.13.1 Primary Fractional Spurs
        2. 9.3.13.2 Sub-Fractional Spurs
      14. 9.3.14 Impact of VCO_DIV on Fractional Spurs
      15. 9.3.15 PLL Phase Noise
        1. 9.3.15.1 , LMX2541SQ3740E Raw Phase Noise Measurement Plot Description
        2. 9.3.15.2 , LMX2541SQ2690 System Phase Noise Plot Description
        3. 9.3.15.3 Phase Noise of PLL
      16. 9.3.16 Impact of Modulator Order, Dithering, and Larger Equivalent Fractions on Spurs and Phase Noise
      17. 9.3.17 Modulator Order
      18. 9.3.18 Programmable Output Power with On/Off
      19. 9.3.19 Loop Filter
      20. 9.3.20 Internal VCO Digital Calibration Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 External VCO Mode
      2. 9.4.2 Digital FSK Mode
    5. 9.5 Programming
      1. 9.5.1 General Programming Information
    6. 9.6 Register Maps
      1. 9.6.1 Register R7
        1. 9.6.1.1  Register R13
          1. 9.6.1.1.1 VCO_DIV_OPT[2:0]
        2. 9.6.1.2  Register R12
        3. 9.6.1.3  Register R9
        4. 9.6.1.4  Register R8
          1. 9.6.1.4.1 AC_TEMP_COMP[4:0]
        5. 9.6.1.5  Register R6
          1. 9.6.1.5.1 RFOUT[1:0] - RFout enable pin
          2. 9.6.1.5.2 DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout
        6. 9.6.1.6  Register R5
          1. 9.6.1.6.1 FL_TOC[13:0] -- Time Out Counter for FastLock
          2. 9.6.1.6.2 FL_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
          3. 9.6.1.6.3 FL_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
          4. 9.6.1.6.4 FL_CPG[4:0] -- Charge Pump Current for Fastlock
        7. 9.6.1.7  Register R4
          1. 9.6.1.7.1 OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking
          2. 9.6.1.7.2 VCO_DIV[5:0] - VCO Divider
          3. 9.6.1.7.3 R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3
          4. 9.6.1.7.4 R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4
          5. 9.6.1.7.5 C3_LF[3:0] -- Value for C3 in the Internal Loop Filter
          6. 9.6.1.7.6 C4_LF[3:0] -- Value for C4 in the Internal Loop Filter
        8. 9.6.1.8  Register R3
          1. 9.6.1.8.1  MODE[1:0] -- Operational Mode
          2. 9.6.1.8.2  Powerdown -- Powerdown Bit
          3. 9.6.1.8.3  XO - Crystal Oscillator Mode Select
          4. 9.6.1.8.4  CPG[4:0] -- Charge Pump Current
          5. 9.6.1.8.5  MUX[3:0] -- Multiplexed Output for Ftest/LD Pin
          6. 9.6.1.8.6  CPP - Charge Pump Polarity
          7. 9.6.1.8.7  OSC2X-- OSCin Frequency Doubler
          8. 9.6.1.8.8  FDM - Extended Fractional Denominator Mode Enable
          9. 9.6.1.8.9  ORDER[2:0] -- Delta-Sigma Modulator Order
          10. 9.6.1.8.10 DITH[1:0] -- Dithering
          11. 9.6.1.8.11 CPT - Charge Pump TRI-STATE
          12. 9.6.1.8.12 DLOCK[2:0] - Controls for Digital Lock Detect
          13. 9.6.1.8.13 FSK - Frequency Shift Keying
        9. 9.6.1.9  Register R2
          1. 9.6.1.9.1 PLL_DEN[21:0] -- Fractional Denominator
        10. 9.6.1.10 Registers R1 and R0
          1. 9.6.1.10.1 PLL_R[11:0] -- PLL R Divider Value
          2. 9.6.1.10.2 PLL_N[17:0] PLL N Divider Value
          3. 9.6.1.10.3 PLL_NUM[21:0] -- Fractional Numerator
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Determining the Best Frequency Option of the LMX2541 to Use
      2. 10.1.2 RFout Output Power Test Setup
      3. 10.1.3 Phase Noise Measurement Test Setup
        1. 10.1.3.1 PLL Phase Noise Measurement
          1. 10.1.3.1.1 PLL Phase Noise Measurement - 1/f Noise
          2. 10.1.3.1.2 PLL Phase Noise Measurement - Flat Noise
        2. 10.1.3.2 VCO Phase Noise Measurement
        3. 10.1.3.3 Divider Phase Noise Measurement
      4. 10.1.4 Input and Output Impedance Test Setup
        1. 10.1.4.1 OSCin Input Impedance Measurement
        2. 10.1.4.2 ExtVCOin Input Impedance Measurement
        3. 10.1.4.3 RFout Output Impedance Measurement
      5. 10.1.5 ExtVCOin (NOT OSCin) Input Sensitivity Test Setup
      6. 10.1.6 OSCin Input Sensitivity Test Setup
        1. 10.1.6.1 Input Sensitivity Test Procedure
        2. 10.1.6.2 OSCin Slew Rate Tests
      7. 10.1.7 Typical Connections
        1. 10.1.7.1 Full Chip Mode, Differential OSCin
        2. 10.1.7.2 External VCO Mode, Single-Ended OSCin, RFout Pin not Used
        3. 10.1.7.3 OSCin/OSCin* Connections
          1. 10.1.7.3.1 Single-Ended Operation
          2. 10.1.7.3.2 Differential Operation
          3. 10.1.7.3.3 Crystal Mode Operation
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Configuring the LMX2541 for Optimal Performance
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NJK|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The LMX2541 is a low-noise synthesizer that can be used with the internal VCO or with an external VCO. The functional description gives more details on this.

9.2 Functional Block Diagrams

LMX2541 30073322.gif
Figure 24. System Block Diagram
LMX2541 30073301.gifFigure 25. Functional Block Diagram

9.3 Feature Description

The LMX2541 is a low power, high performance frequency synthesizer system which includes a PLL, Partially Integrated Loop Filter, VCO, VCO Divider, and Programmable Output Buffer. There are three basic modes that the device can be configured in: Full Chip Mode, External VCO Mode, and Divider Only Mode. Full chip mode is intended to be used with the internal VCO and PLL. There is also the option of External VCO mode, which allows the user to connect their own external VCO. Finally, there is Divider only, which is just the VCO divider and output buffer. The active blocks for these modes are described in Table 10:

Table 10. Active Blocks

MODE AVAILABLE BLOCKS
PLL LOOP
FILTER
VCO VCO
DIVIDER
OUTPUT
BUFFER
Full
Chip
Yes Yes Yes Yes Yes
External
VCO
Yes No No Yes Yes
Divider
Only
No No No Yes Yes

9.3.1 PLL Reference Oscillator Input Pins

There are three basic ways that the OSCin/OSCin* pins may be configured as shown in the table below:

MODE DESCRIPTION XO BIT
Crystal Device is used with a crystal oscillator 1
Single
Ended
Device is driven with a single-ended source, such as a TCXO. 0
Differential Use this mode when driving with a differential signal, such as an LVDS signal. 0

In addition to the way that the OSCin/OSCin* pins are driven, there are also bits that effect the frequency that the chip uses. The OSC_FREQ word needs to be programmed correctly, or the VCO may have issues locking to the proper frequency, because the VCO frequency calibration is based on this word.

Table 11. Word Name and Function

WORD NAME FUNCTION
OSC_FREQ This needs to be set correctly if the internal VCO is used for proper calibration.
OSC2X This allows the oscillator frequency to be doubled. The R divider is bypassed in this case.

Higher slew rates tend to yield the best fractional spurs and phase noise, so a square wave signal is best for OSCin. Single ended mode and differential mode have similar results if a square wave is used to drive the OSCin pin. If using a sine wave, higher frequencies tend to work better due to their higher slew rates.

9.3.2 PLL R Divider

The R divider divides the OSCin frequency down to the phase detector frequency. If the doubler is enabled, then the R divider is bypassed.

9.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the R and N dividers and generates a correction current corresponding to the phase error. This charge pump current is software programmable to 32 different levels. The phase detector frequency, fPD, can be calculated as follows:

Equation 1. fPD = fOSCin / R

9.3.4 PLL N Divider and Fractional Circuitry

The N divider in the LMX2541 includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to 4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion, PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programmable. So in general, the total N divider value, N, is determined by:

Equation 2. N = PLL_N + PLL_NUM / PLL_DEN

The order of the delta-sigma modulator is programmable from integer mode to fourth order. There are also several dithering modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

9.3.5 Partially Integrated Loop Filter

The LMX2541 integrates the third pole (formed by R3_LF and C3_LF) and fourth pole (formed by R4_LF and C4_LF) of the loop filter. The values for these integrated components can be programmed independently through the MICROWIRE interface. The larger the values of these components, the stronger the attenuation of the internal loop filter. The maximum attenuation can be achieved by setting the internal resistors and capacitors to their maximum value and the minimum attenuation can be attained by setting all of these to their minimum setting. This partially integrated loop filter can only be used in full chip mode.

LMX2541 30073304.gifFigure 26. Partially Integrated Loop Filter

9.3.6 Low Noise, Fully Integrated VCO

The LMX2541 includes a fully integrated VCO, including the inductors. The VCO (Voltage Controlled Oscillator) takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related to the other frequencies and divider values as follows:

Equation 3. fVCO = fPD × N = fOSCin × N / R

In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the VCO frequency range is divided into many different frequency bands. This creates the need for frequency calibration in order to determine the correct frequency band given a desired output frequency. The frequency calibration routine is activated any time that the R0 register is programmed. It is important that the OSC_FREQ word is set correctly to have this work correctly.

The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated any time the R0 register is programmed. The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much without being re-calibrated, some minor phase noise degradation could result. For applications where this is an issue, the AC_TEMP_COMP word can be used to sacrifice phase noise at room temperature in order to improve the VCO phase noise over all temperatures. The maximum allowable drift for continuous lock, ΔTCL, is stated in the electrical specifications. For this part, a number of +125 C means the part will never lose lock if the part is operated under recommended operating conditions.

9.3.7 Programmable VCO Divider

The VCO divider can be programmed to any value from 2 to 63 as well as bypass mode if device is in full chip mode. In external VCO mode or divider mode, all values except bypass mode can be used for the VCO divider. The VCO divider is not in the feedback path between the VCO and the PLL and therefore has no impact on the PLL loop dynamics. After this programmable divider is changed, it may be beneficial to reprogram the R0 register to recallibrate the VCO . The frequency at the RFout pin is related to the VCO frequency and divider value, VCO_DIV, as follows:

Equation 4. fRFout = fVCO / VCO_DIV

When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Also, it may be beneficial for VCO phase noise to reprogram the R0 register to recalibrate the VCO if the VCO_DIV value is changed from bypass to divided, or vice-versa.

The duty cycle for this divider is always 50%, even for odd divide values. Because of the architecture of this divider that allows it to work to high frequencies and always have a 50% duty cycle, there are a few extra considerations:

  • In divider only mode, there must be five clock cycles on the ExtVCOin pin after the divide value is programmed in order to cause the divide value to properly changed. It is fine to use more than 5 clock cycles for this purpose.
  • For a divide of 4 or 5 ONLY, the R4 register needs to be programmed one more time after the device is fully programmed in order synchronize the divider. Failure to do so will cause the VCO divider to divide by the wrong value. Furthermore, if the VCO signal ever goes away, as is the case when the part is powered down, it is necessary to reprogram the R4 register again to re-synchronize the divider. Furthermore, if the R0 register is ever programmed in full chip mode, it is also necessary to reprogram the R4 register.

9.3.8 Programmable RF Output Buffer

The output power at the RFout pin can be programmed to various levels as well as on and off states. The output state of this pin is controlled by the RFoutEN pin as well as the RFOUT word. The RF output buffer can be disabled while still keeping the PLL in lock. In addition to this, the actual output power level of this pin can be adjusted using the VCOGAIN, DIVGAIN, and OUTTERM programming words. The reader should note that VCOGAIN controls the gain of the VCO buffer, not the tuning constant in of the VCO.

9.3.9 Powerdown Modes

The LMX2541 can be powered up and down using the CE pin or the POWERDOWN bit. When the device is powered down, the programming and VCO calibration information is retained, so it is not necessary to re-program the device when the device comes out of the powered down state (The one exception is when the VCO_DIV value is 4 or 5, which has already been discussed.). The following table shows how to use the bit and pin.

CE PIN POWERDOWN BIT DEVICE STATE
Low Don't Care Powered Down
High 0 Powered Up
1 Powered Down

The device can be programmed in the powerdown state. However, the VCO frequency needs to be changed when the device is powered up because the VCO calibration does not run in the powerdown state. Also, the special programming for VCO_DIV = 4 or 5 has to be done when the part is powered up. In order for the CE pin to properly power the device down when it is held low, the all registers in the device need to have been programmed at least one time.

9.3.10 Fastlock

The LMX2541 includes the Fastlock feature that can be used to improve the lock times. When the frequency is changed, a timeout counter is used to engage the fastlock for a programmable amount of time. During the time that the device is in Fastlock, the FLout pin changes from high impedance to low, thus switching in the external resistor R2pLF with R2_LF as well as changing the internal loop filter values for R3_LF and R4_LF.

LMX2541 30073305.gifFigure 27. Fastlock Schematic

Table 12 shows the charge pump gain, loop filter resistors, and FLout pin change between normal operation and Fastlock.

Table 12. Normal Operation vs Fastlock

PARAMETER NORMAL
OPERATION
FASTLOCK
Charge Pump Gain CPG FL_CPG
Loop Filter Resistor R3_LF R3_LF FL_R3_LF
Loop Filter Resistor R4_LF R4_LF FL_R4_LF
FLout Pin High
Impedance
Low

Once the loop filter values and charge pump gain are known for normal mode operation, they can be determined for fastlock operation as well. In normal operation, one cannot use the highest charge pump gain and still use fastlock because there will be no larger current to switch in. If the resistors and the charge pump current are done simultaneously, then the phase margin can be preserved while increasing the loop bandwidth by a factor of K as shown in the following table:

PARAMETER SYMBOL CALCULATION
Charge pump gain in Fastlock FL_CPG Typically choose to be the largest value.
Loop Bandwidth Multiplier K K =
sqrt (FL_CPG/CPG)
Internal Loop Filter Resistor FL_R3_LF FL_R3_LF =
R3_LF / K
Internal Loop Filter Resistor FL_R4_LF FL_R4_LF =
R4_LF / K
External Loop Filter Resistor R2pLF R2pLF =
R2_LF / (K - 1)

9.3.11 Lock Detect

The Ftest/LD pin of the LMX2541 can be configured to output a signal that gives an indication for the PLL being locked. There are two styles of lock detect; analog and digital. The analog lock detect signal is more of a legacy feature and consists a series of narrow pulses that correspond to when the charge pump comes on. These pulses can be integrated with an external RC filter to create generate a lock detect signal. Analog lock detect can be configured in a push-pull output or an open drain output. The analog open drain lock detect signal can be integrated with a similar RC filter and requires an additional pullup resistor. This pullup resistor can be much larger than the resistor in the RC filter in order to make unbalanced time constants for improved sensitivity.

The digital lock detect function can also be selected for the Ftest/LD pin to give a logic level indication of lock or unlock. The digital lock detect circuitry works by comparing the difference between the phase of the inputs to the phase detector with a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less than ε for 5 consecutive phase detector cycles. Once in lock (Lock = HIGH), the RC delay is changed to δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater than δ. The values of ε and δ are programmable with the DLOCK word.

LMX2541 30073306.gifFigure 28. Lock Detect

9.3.12 Current Consumption

The current consumption of the LMX2541 has many factors that influence it. Determining the current consumption for the entire device involves knowing which blocks are powered up and adding their currents together. The current in the electrical specifications gives some typical cases, but there could be some variation over factors such as the phase detector frequency. Also, the output buffer current can be impacted by the software controllable settings. By subtracting or adding combinations of the currents for the RFout buffer and VCO divider, the current consumption for the device can be estimated for any usable configuration. The currents for the buffer and VCO divider are as follows:

BLOCK CURRENT (mA)
RF Output Buffer ~ 40
(See Programmable Output Power with On/Off)
VCO Divider 32

9.3.13 Fractional Spurs

9.3.13.1 Primary Fractional Spurs

The primary fractional spurs occur at multiples of the channel spacing and can change based on the fraction. For instance, if the phase detector frequency is 10 MHz, and the channel spacing is 100 kHz, then this could be achieved using a fraction of 1/100. The fractional spurs would be at offsets that are multiples 100 kHz.

9.3.13.2 Sub-Fractional Spurs

Sub-fractional spurs occur at sub-multiples of the channel spacing, Fch. For instance, in the above example, there could be a sub-fractional spur at 50 kHz. The occurrence of these spurs is dependent on the modulator order. Integer mode and the first order modulator never have sub-fractional spurs. If the fractional denominator can be chosen to avoid factors of 2 or 3, then there will also be no sub-fractional spurs. Sub-fractional spurs get worse for higher order modulators. Dithering tends to reduce sub-fractional spurs at the expense of increasing PLL phase noise. Table 13 provides guidance on predicting sub-fractional spur offset frequencies.

Table 13. Sub-Fractional Spur Offset Frequencies
vs.
Modulator Order and Fractional Denominator Factors

ORDER FRACTIONAL DENOMINATOR FACTORS
NO FACTOR of 2 or 3 FACTOR of 2 but not 3 FACTOR of 3 but not 2 FACTOR of 2 and 3
Integer Mode None None None None
1st Order Modulator None None None None
2nd Order Modulator None Fch/2 None Fch/2
3rd Order Modulator None Fch/2 Fch/3 Fch/6
4th Order Modulator None Fch/4 Fch/3 Fch/12

9.3.14 Impact of VCO_DIV on Fractional Spurs

Because the fractional and sub-fractional spur levels do not depend on output frequency, there is a big benefit to division. In general, every factor of 2 gives a 6 dB improvement to fractional spurs. Also, because the spur offset frequency is not divided, the channel spacing at the VCO can be also increased to improve the spurs. However, if the on-chip VCO is used, crosstalk can cause spurs at a frequency of fRFout mod fPD. Consider the following example of a 50 MHz phase detector frequency and VCO_DIV = 2. If the VCO is at 3000.1 MHz and divided by 2 to get 1500.05 MHz, there will be a spur at an offset of 50 kHz (1500.05 MHz mod 50 MHz). However, if the VCO frequency is at 3050.1 MHz, the output will be at 1525.05 MHz, but the spur will be at a much farther offset that can easily be filtered by the loop filter of 25.05 MHz (1525.05 MHz mod 50 MHz).

9.3.15 PLL Phase Noise

9.3.15.1 Figure 6, LMX2541SQ3740E Raw Phase Noise Measurement Plot Description

The above plot demonstrates the PLL phase noise of the LMX2541SQ3700E operating at 3700 MHz output frequency, phase detector frequency of 100 MHz, and charge pump gain of 32X. The loop bandwidth was made as wide as possible to fully expose the PLL phase noise and reference source was a 100 MHz Wenzel crystal. This measurement was done in integer mode. To better understand the impact of using fractional mode, consult the applications section.

The measured noise is the sum of the PLL 1/f noise and noise floor. At offsets below 1 kHz, the PLL 1/f noise dominates and changes at a rate of 10 dB/decade. The noise at 1 kHz is dominated by this 1/f noise and has a value of -103 dBc/Hz. In the 100 - 200 kHz offset range, the noise is -113.7 dBc/Hz and is dominated by the PLL noise floor. It can be shown that if the effects of the loop filter peaking and the 1/f noise are subtracted away from this measurement, it would be about 0.6 dB better.

If the phase detector frequency is changed with the VCO frequency held constant, the PLL noise floor will change, but the 1/f noise will remain the same. If the VCO frequency is changed, both the 1/f noise and PLL noise floor change at a rate of 20 dB/decade.

9.3.15.2 Figure 29, LMX2541SQ2690 System Phase Noise Plot Description

For this plot, a third order modulator with dithering disabled was used with a fractional denominator of 500000. The charge pump gain was 32X and the loop filter components were C1 = 2.2 nF, C2 = 22 nF, R2 = 470 Ω. The internal loop filter components were C3_LF = 20 pF, C4_LF = 100 pF, R3_LF = 1 kΩ, R4_LF = 200 Ω. The VCO frequency is 2720.1 MHz. The OSCin signal was a 500 MHz differential LVPECL output of the LMK04033.

9.3.15.3 Phase Noise of PLL

Disregarding the impact of reference oscillator noise, loop filter resistor thermal noise, and loop filter shaping, the phase noise of the PLL can be decomposed into three components: flicker noise, flat noise, and fractional noise. These noise sources add in an RMS sense to produce the total PLL noise. In other words:

Equation 5. LPLL(f) = 10·log(10(LPLL_flat(f) / 10 ) + 10(LPLL_flicker (f) / 10 )+ 10(LPLL_fractional(f) / 10 )

Table 14. Potential Influencing Factors

SYMBOL POTENTIAL INFLUENCING FACTORS
f fVCO fPD KPD FRAC
LPLL_flat(f) No Yes Yes Yes No
LPLL_flicker(f) Yes Yes No Yes No
LPLL_fractional(f) Yes No Yes No Yes

The preceding table shows which factors of offset frequency (f), VCO frequency (fVCO), phase detector frequency (fPD), charge pump gain (KPD), and the fractional settings (FRAC) can potentially influence each phase noise component. The fractional settings include the fraction, modulator order, and dithering.

For the flat noise and flicker noise, it is possible to normalize each of these noise sources into a single index. By normalizing these noise sources to an index, it makes it possible to calculate the flicker and flat noise for an arbitrary condition. These indices are reported in the electrical characteristics section and in the typical performance curves.

Table 15. Noise Component

NOISE COMPONENT INDEX RELATIONSHIP
LPLL_flat(f) LNPLL_flat
(1 Hz)
LPLL_flat(f) =
LNPLL_flat(1 Hz)
+ 20·log(N) + 10·log(fPD)
LPLL_flicker(f) LNPLL_flicker
(10 kHz)
LPLL_flicker(f) =
LNPLL_flicker(10 kHz)
- 10·log(10 kHz / f) + 20·log( fVCO / 1 GHz )

The flat noise is dependent on the PLL N divider value (N) and the phase detector frequency (fPD) and the 1 Hz Normalized phase noise ( LNPLL_flat(1 Hz) ). The 1 Hz normalized phase noise can also depend on the charge pump gain as well. In order to make an accurate measurement of just the flat noise component, the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. This becomes easier to measure for lower phase detector frequencies.

The flicker noise, also known as 1/f noise, can be normalized to 1 GHz carrier frequency and 10 kHz offset, LNPLL_flicker(10 kHz). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure the flicker noise it is important to use a high phase detector frequency and a clean crystal to make it such that this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used.

An alternative way to interpret the flicker noise is the 1/f noise corner, fcorner. This would be the offset frequency where the flat noise and flicker noise are equal. This corner frequency changes as a function of the phase detector frequency and can be related to the flat and flicker noise indices as shown below.

Equation 6. fcorner = 10( (LNPLL_flicker(10 kHz) - LNPLL_flat(1 Hz) - 140) / 10 ) × fPD

Based on the values for LNPLL_flicker(10 kHz) and LNPLL_flat(1Hz) as reported in the electrical specifications, the corner frequency can be calculated. For example, one of the plots in the typical performance characteristics shows the phase noise with a 100 MHz phase detector frequency and 32X charge pump gain. In this case, this corner frequency works out to be 0.000123 × 100 MHz = 12.3 kHz.

KPD LNPLL_flicker(10 kHz) LNPLL_flat(1 Hz) fcorner
1X -116.0 dBc/Hz -220.8 dBc/Hz 0.000302 × fPD
32X -124.5 dBc/Hz -225.4 dBc/Hz 0.000123 × fPD

For integer mode or a first order modulator, there is no fractional noise (disregarding fractional spurs). For higher order modulators, the fractional engine may or may not add significant phase noise depending on the fraction and choice of dithering.

9.3.16 Impact of Modulator Order, Dithering, and Larger Equivalent Fractions on Spurs and Phase Noise

To achieve a fractional N value, an integer N divider is modulated between different values. This gives rise to three main degrees of freedom with the LMX2541 delta-sigma engine: the modulator order, dithering, and the way that the fractional portion is expressed. The first degree of freedom, the modulator order, can be selected as zero (integer mode), one, two, three, or four. One simple technique to better understand the impact of the delta-sigma fractional engine on noise and spurs is to tune the VCO to an integer channel and observe the impact of changing the modulator order from integer mode to a higher order. A higher fractional modulator order in theory yields lower primary fractional spurs. However, this can also give rise to sub-fractional spurs in some applications. The second degree of freedom is dithering. Dithering seeks to improve the sub-fractional spurs by randomizing the sequence of N divider values. In theory, a perfectly randomized sequence would eliminate all sub-fractional spurs, but add phase noise by spreading the energy that would otherwise be contained in the spurs. The third degree of freedom is the way that the fraction is expressed. For example, 1/10 can be expressed as a larger equivalent fraction of 100000/1000000. Using larger equivalent fractions tends to increase randomization similar to dithering. In general, the very low phase noise of the LMX2541 exposes the modulator noise when dithering and large fractions are used, so use these with caution. The avid reader is highly encouraged to read application note 1879 for more details on fractional spurs. The following table summarizes the relationships between spur types, phase noise, modulator order, dithering and fractional expression.

NOISE / SPUR TYPE ACTION
INCREASE
MODULATOR
ORDER
INCREASE
DITHERING
USING
LARGER
EQUIVALENT
FRACTIONS
Phase Noise WORSE
(But only for larger fractions or more dithering)
WORSE WORSE
Primary Fractional Spur BETTER NO IMPACT NO IMPACT
Sub-Fractional Spurs WORSE
(Creates more sub
-fractional spurs)
BETTER BETTER

9.3.17 Modulator Order

In general, the fractional mode of the PLL enables the use of a higher phase detector frequency relative to the channel spacing, which enables the in-band noise of the PLL to be lower. The choice of modulator order to be used in fractional mode is based on how much higher fPD can be made relative to the channel spacing and the acceptable spur levels. The LMX2541 has a programmable modulator order which allows the user to make a trade-off between PLL noise and primary and sub-fractional spur performance. The following table provides some general guidelines for choosing modulator order: Note that the spurs due to crosstalk will not be impacted by modulator order.

ORDER GUIDELINES FOR USE
Integer Mode
  • Use if fPD can be made very high without using a fractional N value.
  • Use if it is not desired to make fPD higher using a fractional N value. This could be the case if the loop bandwidth is very narrow and smaller loop filter capacitors are desired.
1st Order Modulator
  • Use 1st order if fPD can be increased by at least a factor of four over the integer case and fractional spur frequencies and levels are acceptable.
  • If the channel spacing is 5 MHz or greater, the 1st order modulator may provide better spur performance than integer mode.
2nd Order Modulator
3rd Order Modulator
4th Order Modulator
  • If the spurs of the 1st order modulator are unacceptable, use a higher order modulator. If the spurious components are due to crosstalk they will not be improved by increasing modulator order. In this case , use the lowest order modulator that gives acceptable performance.
  • Use if the spurs of the 1st order modulator are unacceptable.
  • In general, use the lowest order modulator unless a higher order modulator yields an improvement in primary fractional spurs. If the spurious components are due to crosstalk, they will not be improved by increasing the modulator order.

9.3.18 Programmable Output Power with On/Off

The power level of the RFout pin is programmable, including on/off controls. The RFoutEN pin and RFOUT word can be used to turn the RFout pin on and off while still keeping the VCO running and in lock. In addition to on/off states, the power level can also be programmed in various steps using the VCOGAIN, DIVGAIN, and OUTTERM programming words. There are tables in the Typical Characteristics section that discuss the impact of these words on the output power. In addition to impacting the output power, these words also impact the current consumption of the device. This data was obtained as an average over all frequencies. In general, it is desirable to find the combination of programming words that gives the lowest current consumption for a given output power level. All numbers reported are relative to the case of VCOGAIN = OUTTERM = 12. According to this data, using a VCOGAIN or OUTTERM value of 12 or greater yields only a small increase in output power, but a large increase in current consumption.

Table 16. Change in Current Consumption in Bypass Mode as a Function of VCOGAIN and OUTTERM

VCOGAIN
3 6 9 12 15
OUTTERM 3 -26.0 -22.3 -18.6 -15.1 -11.8
6 -18.5 -15.5 -12.6 -9.7 -6.9
9 -11.1 -9.0 -6.9 -4.7 -2.5
12 -3.8 -2.6 -1.4 +0.0 +1.5
15 +3.3 +3.7 +4.0 +4.5 +5.3

Table 17. Change in Current Consumption in Divided Mode as a Function of DIVGAIN and OUTTERM

DIVGAIN
3 6 9 12 15
OUTTERM 3 -24.4 -21.7 -18.7 -15.9 -13.3
6 -16.2 -14.6 -12.6 -10.1 -8.0
9 -8.3 -7.6 -6.8 -5.0 -3.2
12 -0.5 -0.7 -0.7 +0.0 +1.3
15 +7.1 +6.0 +5.2 +4.9 +5.6

9.3.19 Loop Filter

Loop filter design can be rather complicated, but there are design tools and references available at www.ti.com. The loop bandwidth can impact the size of loop filter capacitors and also how the phase noise is filtered. For optimal integrated phase noise, choose the bandwidth to be about 20% wider than the frequency where the in-band PLL phase noise (as described in PLL Phase Noise) and open loop VCO noise cross. This optimal loop bandwidth may need adjustment depending on the application requirements. Reduction of spurs can be achieved by reducing the loop bandwidth. On the other hand, a wider loop bandwidth may be required for faster lock time. Note that using the integrated loop filter components can lead to a significant restriction on the loop bandwidth and should be used with care. 2 kΩ for R3_LF and R4_LF is a good starting point. If the integrated loop filter restricts the loop bandwidth, then first try to relieve this restriction by reducing the integrated loop filter resistors and then reduce the capacitors only if necessary.

9.3.20 Internal VCO Digital Calibration Time

When the LMX2541 is used in full chip mode, the integrated VCO can impact the lock time of the system. This digital calibration chooses the closest VCO frequency band, which typically gets the device within a frequency error 10 MHz or less of the final settling frequency, although this final frequency error can change slightly between the different options of the LMX2541. Once this digital calibration is finished, this remaining frequency error must settle out, and this remaining lock time is dictated by the loop bandwidth.

Based on measured data, this digital calibration time can be approximated by the following formula:

Equation 7. LockTime = A + B/CLK + C·ΔF + D·( ΔF/CLK )
SYMBOL1 VALUE UNITS
Locktime Varies µs
A 30 μs
B 3800 None
C 0.1 us/MHz
D 2 µs
ΔF Varies MHz
CLK fOSCin / 2
for 0 ≤ OSC_FREQ ≤ 63
fOSCin / 4
for 64 ≤ OSC_FREQ ≤ 127
fOSCin / 8
for 128 ≤ OSC_FREQ
None

For example, consider the LMX2541SQ3320E changing from 3600 to 3400 with an OSCin frequency of 100 MHz. In this case, ΔF = 200 (direction of frequency change does not matter), fOSCin = 100 MHz, and OSC_FREQ=100. The calibration circuitry is run at a clock speed of CLK = 100 MHz / 4 = 25 MHz. When this values are substituted in the formula, the resulting lock time is 218 μs. After this time, the VCO will be within about 10 MHz of the final frequency and this final frequency error will settle out in an analog fashion. This final frequency error can be slightly different depending on which option of the LMX2541 is being used.

9.4 Device Functional Modes

9.4.1 External VCO Mode

The LMX2541 also has provisions to be driven with an external VCO as well. In this mode, the user has the option of using the RFout pin output, although if this pin is used, the VCO input frequency is restricted to 4 GHz. If not used, the RFout pin should be left open. The VCO input is connected to the ExtVCOin pin. Because the internal VCO is not being used, the part option that is being used does not have a large impact on phase noise or spur performance. It is also possible to switch between both Full Chip mode and External VCO mode.

9.4.2 Digital FSK Mode

The LMX2541 supports 2-level digital frequency shift keying (FSK) modulation. The bit rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at least twice the bit rate. This is achieved by changing the N counter rapidly between two states. The fractional numerator and denominator are restricted to a length of 12 bits. The 12 LSB’s of the numerator and denominator set the center frequency, Fcenter, and the 10 MSB’s of the numerator set the frequency deviation, Fdev. The LMX2541 has the ability to switch between two different numerator values based on the voltage at the DATA pin. When DATA is low, the output frequency will be Fcenter – Fdev and when the DATA pin is high the output frequency will be Fcenter + Fdev. A limitation of the FSK mode is the frequency deviation cannot cause the N counter to cross integer boundaries. When using FSK mode, the FDM bit needs to be set to zero.

9.5 Programming

There are several other considerations for programming:

  • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter.
  • A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.
  • After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.
  • When using the part in Full Chip Mode with the Integrated VCO, LE should be kept high no more than 1 us after the programming of the R0 register. Failure to do so may interfere with the digital VCO calibration.
  • If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming.

9.5.1 General Programming Information

The LMX2541 is programmed using several 32-bit registers used to control the LMX2541 operation. A 32-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 28 bits form the data field DATA[27:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. For initial device programming the register programming sequence must be done in the order as shown in the register map. The action of programming register R7 and bringing LE low resets all the registers to default values, including hidden registers. The programming of register R0 is also special for the device when operating in full chip mode because the action of programming either one of these registers activates the VCO calibration.

In addition to changing the values of various words, the programming of certain registers triggers certain events as described in the table below:

PROGRAMMING EVENT EVENT TRIGGERED CONFIGURATIONS
WHERE IT HAS AN IMPACT
SIGNIFICANCE
Action of programming register R7 and bring LE low Resets all registers, including hidden ones, to a default state All This needs to be the first programming step for all configurations. If register R7 is ever programmed again, all programming information will be reset to the default state.
Action of programming register R0 and bringing LE low Activates the VCO calibration Only in Full Chip Mode The VCO calibration tunes the VCO to the correct frequency band and optimizes the phase noise. It is necessary whenever the internal VCO frequency is changed. Also, if the temperature drifts considerably, then this calibration can better optimize the phase noise.
Action of programming register R4 Synchronizes the VCO Divider Only when the RFout pin ins enabled and the VCO divider is set to 4 or 5 Consult the Feature Description for more details.

9.6 Register Maps

The following table lists the registers as well as the order that they should be programmed. Register 7 is programmed first and the action of programming register R7 resets all the registers after the LE pin is pulled to a low state. Register R0 is programmed last because it activates the VCO calibration. The one exception to this is when the VCO_DIV value is 4 or 5. Consult the programming section on VCO_DIV for more details.

Table 18. Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[27:0] C3 C2 C1 C0
R7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VCO_DIV_OPT[2:0] 1 1 0 1
R12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
R9 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1
R8 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 AC_TEMP_COMP[4:0] 1 0 0 0
R6 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VCOGAIN[3:0] OUTTERM[3:0] DIVGAIN[3:0] RFOUT[1:0] 0 1 1 0
R5 1 0 1 FL_CPG[4:0] FL_RF_LF[2:0] FL_R3_LF[2:0] FL_TOC[13:0] 0 1 0 1
R4 C4_LF[3:0] C3_LF[3:0] R4_LF[2:0] R3_LF[2:0] VCO_DIV[5:0] OSC_FREQ[7:0] 0 1 0 0
R3 FSK 0 0 DLOCK[2:0] CPT DITH[1:0] ORDER[2:0] FDM OSC
_2X
CPP MUX[3:0] CPG[4:0] XO POWER
DOWN
MODE[1:0] 0 0 1 1
R2 0 0 0 0 0 1 DEN[21:0] 0 0 1 0
R1 0 0 0 0 PLL_NUM[21:16] PLL_N[17:12] PLL_R[11:0] 0 0 0 1
R0 PLL_NUM[15:0] PLL_N[11:0] 0 0 0 0

9.6.1 Register R7

Although Register 7 has no elective bits to program, it is very important to program this register because the action of doing so with the bit sequence shown in the register map resets all the registers, including hidden registers with test bits that are not disclosed. Register 7 should always be programmed first, because it will reset all other programming information. The register reset occurs only after the LE signal has transitioned from low to high and back to low again.

9.6.1.1 Register R13

This register needs to be programmed only in the event that the RFout pin is being used and VCO_DIV = 1.

9.6.1.1.1 VCO_DIV_OPT[2:0]

This word optimizes the RFout power level based on the VCO_DIV and VCO_GAIN words.

CONDITION VCO_DIV_OPT COMMENTS
RFout Pin Disabled
OR
VCO_DIV>1
OR
VCO_GAIN<13
0 Register R13 Does Not need to be programmed, because 0 is the default.
RFout Pin Enabled
AND
VCO_DIV=1
VCO_GAIN>12
4

9.6.1.2 Register R12

This register needs to be programmed as shown in the register map in the event that the internal VCO is being used. When using external VCO mode, this register does not need to be programmed.

9.6.1.3 Register R9

Program this register as shown in the register map.

9.6.1.4 Register R8

9.6.1.4.1 AC_TEMP_COMP[4:0]

This word optimizes the VCO phase noise for possible temperature drift. When the VCO frequency is changed, the internal tuning algorithm optimizes the phase noise for the current temperature. In fixed frequency applications, temperature drift may lead to sub-optimal phase noise over time. In dynamic frequency applications, the re-tuning of the VCO frequency overcomes this problem because the phase noise is re-optimized each time the VCO frequency is changed. The AC_TEMP_COMP word can be used to optimize the VCO phase noise for temperature drift for these different scenarios. The following table indicates which values of this word should be used for each scenario.

AC_TEMP_COMP APPLICATION TYPE
5 Dynamic Frequency
24 Fixed Frequency
All Other States Invalid

9.6.1.5 Register R6

Register R6 has words that impact the output power of the RFout pin.

9.6.1.5.1 RFOUT[1:0] - RFout enable pin

This word works in combination with the RFoutEN Pin to control the state of the RFout pin.

RFOUT RFoutEN PIN RFout PIN STATE
0 Don't Care Disabled
2 Don't Care Enabled
1 or 3 Low Disabled
High Enabled

9.6.1.5.2 DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout

These three words may be programmed in a value from 0 to 15 and work in conjunction to control the output power level of the RFout pin. Increasing any of these values increases the output power at the expense of higher current consumption of the buffer. Although there may be more than one way to get the same output power, some combinations may have lower current. The typical performance characteristics show these trade-offs. The default setting for all these bits is 12. The value of VCO_DIV determines which two of these three words have an impact.

VCO_DIV BITS that IMPACT POWER
1 (Bypass) OUTTERM, VCOGAIN
>1 (Not Bypass) OUTTERM, DIVGAIN

9.6.1.6 Register R5

This register controls the fastlock mode which enables a wider loop bandwidth when the device is changing frequencies.

9.6.1.6.1 FL_TOC[13:0] -- Time Out Counter for FastLock

When the value of this word is 3 or less, FastLock time out counter is disabled, and the FLout pin can be used for general purpose I/O. When this value is 4 or greater, the time out counter is engaged for the amount of phase detector cycles shown in the table below.

TOC VALUE FLout PIN STATE FASTLOCK ENGAGEMENT TIME
0 High Impedance Disabled
1 Low Always Engaged
2 Low Disabled
3 High Disabled
4 Low Engaged for
4 × 2 Phase Detector Cycles
. . .
16383 Low Engaged for
16383 × 2 Phase Detector Cycles

When this count is active, the FLout Pin is grounded, the FastLock current is engaged, and the resistors R3 and R4 are also potentially changed. The table below summarizes the bits that control various values in and out of FastLock.

FastLock STATE FLout CHARGE PUMP CURRENT R3_LF VALUE R4_LF VALUE
Not Engaged High Impedance CPG R3_LF R4_LF
Engaged Grounded FL_CPG FL_R3_LF FL_R4_LF

9.6.1.6.2 FL_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock

FL_R3_LF VALUE R3 RESISTOR DURING FASTLOCK (kΩ)
0 Low ( 200 Ω )
1 1
2 2
3 4
4 16
5-7 Reserved

9.6.1.6.3 FL_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock

FL_R4_LF VALUE R3 RESISTOR DURING FASTLOCK (kΩ)
0 Low ( 200 Ω )
1 1
2 2
3 4
4 16
5-7 Reserved

9.6.1.6.4 FL_CPG[4:0] -- Charge Pump Current for Fastlock

When FastLock is enabled, this is the charge pump current that is used for faster lock time.

FL_CPG FASTLOCK CHARGE PUMP STATE TYPICAL FASTLOCK CHARGE PUMP CURRENT at 3.3 VOLTS (µA)
0 1X 100
1 2X 200
2 3X 300
3 4X 400
... ... ...
31 32X 3200

9.6.1.7 Register R4

This register controls miscellaneous functions of the device. The action of programming the R4 register also synchronizes the VCO divider, which is necessary when VCO_DIV = 4 or 5.

9.6.1.7.1 OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking

This word is used for the VCO frequency calibration. This word should be set to the OSCin frequency rounded to the nearest MHz.

OSC_FREQ OSCin FREQUENCY
0 Illegal State
1 1 MHz
2 2 MHz
... ...
255 255 MHz
and higher

9.6.1.7.2 VCO_DIV[5:0] - VCO Divider

The output of the VCO is divided by the value of VCO_DIV, which can range from 1 (Bypass Mode) to 63 and all values in between with the limitation that the VCO divider can only be set to bypass mode when the device is operating in full chip mode. When the VCO divider is set to 4 or 5 ONLY, there is one extra programming step required to synchronize the VCO divider. Consult the Feature Description for more details.

VCO_DIV VCO OUTPUT DIVIDE COMMENTS
0 n/a Illegal State
1 Bypass Mode This state only available for MODE=Full Chip Mode
2 Divide by 2
3 Divide by 3
4 Divide by 4 Extra programming is required for divide by 4 and divide by 5 only. Refer to the Feature Description for more details.
5 Divide by 5
6 Divide by 6
... ...
62 Divide by 62
63 Divide by 63

9.6.1.7.3 R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3

This word controls the state of the internal loop filter resistor R3_LF when the device is in Full Chip Mode and Fastlock is not active.

R3_LF VALUE R3 RESISTOR DURING FASTLOCK (kΩ)
0 Low ( 200 Ω )
1 1
2 2
3 4
4 16
5-7 Reserved

9.6.1.7.4 R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4

This word controls the state of the internal loop filter resistor R4_LF when the device is in Full Chip Mode and Fastlock is not active.

R4_LF VALUE R3 RESISTOR DURING FASTLOCK (kΩ)
0 Low ( 200 Ω )
1 1
2 2
3 4
4 16
5-7 Reserved

9.6.1.7.5 C3_LF[3:0] -- Value for C3 in the Internal Loop Filter

This word controls the state of the internal loop filter resistor C3_LF when the device is Full Chip Mode.

C3_LF C3 (pF)
0 0
1 1
2 5
3 6
4 10
5 11
6 15
7 16
8 20
9 21
10 25
11 26
12 30
13 31
14 35
15 36

9.6.1.7.6 C4_LF[3:0] -- Value for C4 in the Internal Loop Filter

This word controls the state of the internal loop filter resistor C4_LF when the device is Full Chip Mode.

C4_LF C4 (pF)
0 0
1 5
2 20
3 25
4 40
5 45
6 60
7 65
8 100
9 105
10 120
11 125
12 140
13 145
14 160
15 165

9.6.1.8 Register R3

This register controls miscellaneous features of the device.

9.6.1.8.1 MODE[1:0] -- Operational Mode

The LMX2541 can be run in several operational modes as listed in the table below:

MODE NAME DIVIDER PLL VCO
0 Full Enabled Enabled Enabled
1 External VCO Enabled Enabled Disabled
2 Divider Only Enabled Disabled Disabled
3 Test (Reserved) Enabled Enabled Enabled

9.6.1.8.2 Powerdown -- Powerdown Bit

Enabling this bit powers down the entire device, although register and VCO calibration information is retained.

9.6.1.8.3 XO - Crystal Oscillator Mode Select

When this bit is enabled, a crystal with appropriate load capacitors can be attached between the OSCin and OSCin* pins in order to form a crystal oscillator.

9.6.1.8.4 CPG[4:0] -- Charge Pump Current

This word programs the charge pump current gain. The current is programmable between 100 uA and 3.2 mA in 100 uA steps.

CPG CHARGE PUMP STATE TYPICAL CHARGE PUMP CURRENT (µA)
0 1X 100
1 2X 200
2 3X 300
3 4X ...
... ...
31 32X 3200

9.6.1.8.5 MUX[3:0] -- Multiplexed Output for Ftest/LD Pin

The MUX[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be high when the device is in lock, and low otherwise. The output voltage level of the Ftest/LD is not equal to the supply voltage of the device, but rather is given by VOH and VOL in the electrical characteristics specification.

Because the Ftest/LD pin is close to the OSCin pin, the state of this pin can have an impact on the performance of the device. If any of the diagnostic modes (8-13) are used, the OSCin sensitivity can be severely degraded, so these should only be used for diagnostic purposes. The fractional spurs can also be impacted a little by the MUX programming word. The Push-Pull digital lock detect modes, like mode 3, tend to have the best fractional spurs, so these states are recommended, even if the digital lock detect function is not needed.

MUX OUTPUT TYPE FUNCTION COMMENTS
0 High Impedance Disabled GENERAL PURPOSE I/O MODES
1 Push-Pull Logical High State
2 Push-Pull Logical Low State
3 Push-Pull Digital Lock Detect LOCK DETECT MODES
Consult Feature Description for more details
State 3 is recommended for optimal spurious performance.
4 Push-Pull Inverse Digital Lock Detect
5 Open Drain Digital Lock Detect
6 Open Drain Analog Lock Detect
7 Push-Pull Analog Lock Detect
8 Push-Pull N Divider DIAGNOSTIC MODES
These allow the user to view the outputs of the N divider, R divider, and phase frequency detector (PFD) and are intended only for diagnostic purposes. Typically, the output is narrow pulses, but when the output is divided by 2, there is a 50% duty cycle. The use of these modes (including R Divider) can degrade the OSCin sensitivity.
9 Push-Pull N Divider / 2
10 Push-Pull R Divider
11 Push-Pull R Divider / 2
12 Push-Pull PFD Up
13 Push-Pull PFD Down
14-15 N/A Reserved

9.6.1.8.6 CPP - Charge Pump Polarity

This bit sets the polarity of the phase detector.

CPP CHARGE PUMP POLARITY TYPICAL APPLICATIONS
0 Negative Full Chip Mode
External VCO Mode with an inverting active loop filter.
1 Positive External VCO Mode with a passive loop filter.

9.6.1.8.7 OSC2X-- OSCin Frequency Doubler

Enabling this bit doubles the OSCin frequency. This is useful in achieving a higher phase detector frequency to improve PLL phase noise, push out noise from the delta-sigma modulator, and sometimes reduce fractional spurs . Note that when this bit is enabled, the R divider is bypassed.

OSC_2X STATE
0 Normal
1 OSCin frequency is doubled

9.6.1.8.8 FDM - Extended Fractional Denominator Mode Enable

Enabling this bit allows the fractional numerator and denominator to be expanded from 10 bits to 22 bits. In 10-bit mode, only the first 10 bits of the fractional numerator and denominator are considered. When using FSK mode, this bit has to be disabled.

FDM FRACTIONAL MODE
0 10-bit
1 (Default) 22-bit

9.6.1.8.9 ORDER[2:0] -- Delta-Sigma Modulator Order

This word determines the order of the delta-sigma modulator in the PLL. In general, higher order fractional modulators tend to reduce the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction of the channel spacing. The optimal choice of modulator order is very application specific, however, a third order modulator is a good starting point. The first order modulator has no analog compensation or dithering

ORDER DELTA-SIGMA
MODULATOR
MODE COMMENTS
0 Disabled Integer Allows larger N Counter
1 First Order Fractional This has no analog compensation or dithering
2 Second Order Traditional Delta-Sigma Operation
3 Third Order
4 Fourth Order
5-7 Illegal States n/a n/a

9.6.1.8.10 DITH[1:0] -- Dithering

Dithering randomizes the delta-sigma modulator output. This reduces sub-fractional spurs at the expense of adding phase noise. In general, it is recommended to keep the dithering strength at None or Weak for most applications. Dithering should never be used when the device is used in integer mode or a first order modulator. When using dithering with the other delta-sigma modulator orders, it is beneficial to disable it in the case where the fractional numerator is zero, because it can actually create sub-fractional spurs.

DITH DITHERING STRENGTH
0 Weak
1 Medium
2 Strong
3 Disabled

9.6.1.8.11 CPT - Charge Pump TRI-STATE

When this bit is enabled, the charge pump is at TRI-STATE. The TRI-STATE mode could be useful for open loop modulation applications or as diagnostic tool for measuring the VCO noise, but is generally not used.

CPT CHARGE PUMP
0 Normal Operation
1 TRI-STATE

9.6.1.8.12 DLOCK[2:0] - Controls for Digital Lock Detect

This word controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In order to indicate the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time offset between the R and N counter outputs is less than ε. This will cause the Ftest/LD pin output to go high. Once lock is indicated, it will remain in this state until the time offset between the R and N counter outputs exceeds δ. For this device, ε and δ are the same. If the OSCin signal goes away, the digital lock detect circuit will reliably indicate an unlocked condition. Consult the Feature Description for more details. A larger window size makes the lock detect circuit less sensitive, but may be necessary in some situations to reduce chattering.

DLOCK WINDOW SIZE
(ε and δ)
0
(Default)
3.5
1 5.5
2 7.5
3 9.5
4 11.5
5 13.5
6 -7 Reserved

There are restrictions when using digital lock detect, based on the phase detector frequency (fPD), Modulator Order (ORDER), and VCO frequency (fVCO). The first restriction involves a minimum window size (εmin), the second one involves a maximum window size (εmax), and the third involves further restrictions on the maximum phase detector frequency that are implied by the window size that is selected.

The first restriction involves the minimum window size (εmin). This minimum window size cannot be greater than the maximum programmable value of 13.5 ns for valid operation of the digital lock detect. Possible remedies for this solution would be reducing the delta-sigma order, using a higher VCO frequency and using a larger VCO_DIV value, or using analog lock detect.

Equation 8. 13.5 ns ≥ εmin = 2ORDER-1 / fVCO

The second restriction is the maximum window size (εmax). If the calculated maximum window size is less than the minimum programmable window size of 3.5 ns, then this indicates that the digital lock detect cannot be used in this condition. Possible remedies for this could be to decrease the phase detector frequency, use analog lock detect, decrease the delta-sigma order, or decrease the VCO frequency.

Equation 9. 3.5 ns ≤ εmax = 1/fPD - εmin - 2 ns

The third restriction comes from rearranging the equation for εmax.

Equation 10. fPD ≤ 1 / ( εmin + εmax + 2 ns )

In addition to this restriction on the maximum phase detector rate, recall that there are also restrictions on the maximum phase detector rate implied by the electrical specifications ( fPD≤ 104 MHz ) and by the minimum continuous N divider value (fPD ≤ fVCO / NMin).

fVCO ORDER εmin MAXIMUM POSSIBLE PHASE DETECTOR FREQUENCY (MHz)
(MHz) (ns) ε = 3.5 ns ε = 5.5 ns ε = 7.5 ns ε = 9.5 ns ε = 11.5 ns ε = 13.5 ns
All 0 0.0 Min
(104, fVCO / 12)
Min
(104, fVCO / 12)
Min
(104, fVCO / 12)
Min
(87.0, fVCO / 12)
Min
(74.1, fVCO / 12)
Min
(64.5, fVCO / 12)
400 4 20.0 FAIL FAIL FAIL FAIL FAIL FAIL
400 3 10.0 FAIL FAIL FAIL FAIL 26.7 26.7
400 2 5.0 FAIL 30.8 30.8 30.8 30.8 30.8
500 4 16.0 FAIL FAIL FAIL FAIL FAIL FAIL
500 3 8.0 FAIL FAIL FAIL 33.3 33.3 33.3
500 2 4.0 FAIL 38.5 38.5 38.5 38.5 38.5
600 4 13.3 FAIL FAIL FAIL FAIL FAIL 31.6
600 3 6.7 FAIL FAIL 40.0 40.0 40.0 40.0
600 2 3.3 46.2 46.2 46.2 46.2 46.2 46.2
1200 4 6.7 FAIL FAIL 63.2 63.2 63.2 63.2
1200 3 3.3 80.0 80.0 80.0 80.0 74.1 64.5
1200 2 1.7 92.3 92.3 92.3 87.0 74.1 64.5
1530 4 5.2 FAIL 80.3 80.3 80.3 74.1 64.5
1530 3 2.6 102.0 102.0 102.0 87.0 74.1 64.5
1530 2 1.3 104.0 104.0 104.0 87.0 74.1 64.5
1800 4 4.4 FAIL 91.8 91.8 87.0 74.1 64.5
1800 3 2.2 104.0 104.0 104.0 87.0 74.1 64.5
1800 2 1.1 104.0 104.0 104.0 87.0 74.1 64.5
2000 4 4.0 FAIL 100.0 100.0 87.0 74.1 64.5
2000 3 2.0 104.0 104.0 104.0 87.0 74.1 64.5
2000 2 1.0 104.0 104.0 104.0 87.0 74.1 64.5
3000 4 2.7 104.0 104.0 104.0 87.0 74.1 64.5
3000 3 1.3 104.0 104.0 104.0 87.0 74.1 64.5
3000 2 0.7 104.0 104.0 104.0 87.0 74.1 64.5
4000 4 2.0 104.0 104.0 104.0 87.0 74.1 64.5
4000 3 1.0 104.0 104.0 104.0 87.0 74.1 64.5
4000 2 0.5 104.0 104.0 104.0 87.0 74.1 64.5

In the previous table, consider the case of operating in integer mode with ORDER=0. For this case, lock detect can theoretically work for all VCO frequencies provided that the phase detector frequency does not violate the maximum possible value. For instance, it would be an invalid condition to operate in integer mode with a VCO frequency of 900 MHz and a phase detector frequency of 100 MHz because 100 MHz exceeds the limit of 900 MHz/12 = 75 MHz. If the phase detector was lowered to 75 MHz to meet this restriction, then this condition would be valid provided that the window size was programmed to be 9.5 ns or less.

Consider another example of a 400 MHz VCO frequency with a fourth order modulator. Because the minimum window size of 20 ns is above the maximum programmable value of 13.5 ns, digital lock detect cannot be used in this configuration. If the modulator order was reduced to 2nd order, then it would function provided that the phase detector frequency was less 30.8 MHz.

9.6.1.8.13 FSK - Frequency Shift Keying

This bit enables a binary FSK modulation mode using the PLL N counter. Consult the applications section for more details.

FSK FSK MODE
0 Disabled
1 Enabled

9.6.1.9 Register R2

This word contains all the bits of the fractional denominator. These bits apply if the device is being used fractional mode.

9.6.1.9.1 PLL_DEN[21:0] -- Fractional Denominator

These bits determine the fractional denominator.

PLL_DEN[21:0]
Fractional
Denominator
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
... . . . . . . . . . . . . . . . . . . . . . .
4194303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

9.6.1.10 Registers R1 and R0

Both registers R1 and R0 contain information for the PLL R counter, N counter, and fractional numerator. The action of programming register R0, even to the same value, runs the VCO calibration when the device has the internal VCO operating. There are some programming words that are split across these two registers.

9.6.1.10.1 PLL_R[11:0] -- PLL R Divider Value

The R divider divides the OSCin signal. Note that if the doubler is enabled, the R divider is bypassed.

PLL_R[11:0]
0 Illegal State
1 0 0 0 0 0 0 0 0 0 0 0 1
2 0 0 0 0 0 0 0 0 0 0 1 0
3 0 0 0 0 0 0 0 0 0 0 1 1
... ... ... ... ... ... ... ... ... ... ... ... ...
4095 1 1 1 1 1 1 1 1 1 1 1 1

9.6.1.10.2 PLL_N[17:0] PLL N Divider Value

When using integer mode, the PLL N divider value is split up into two different locations. In fractional mode, only the 12 LSB bits of the N counter are used. Based on the order of the modulator, the range is shown in the table below.

PLL_N[17:12] PLL_N[11:0]
<12 Integer
Mode
Divide Values below 12 are prohibited
12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
... . . . . . . . . . . . . . . . . . .
262143 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
12 Fractional Mode Possible with first order modulator only
13-14 Possible with first or second order modulator
15-18 Possible with first, second, or third order modulators only
19 x x x x x x 0 0 0 0 0 0 0 1 0 0 1 1
... . . . . . . . . . . . . . . . . . .
4087 x x x x x x 1 1 1 1 1 1 1 1 0 1 1 1
4088
-4091
Possible with a first, second, or third order modulator only
4092-4093 Possible with a first or second order modulator only
4094 Possible with a first order modulator only

Note that the N divider value has a minimum value, NMin, which is implied by the modulator order. NMin is 12 for integer mode and a first order modulator, 13 for a 2nd order modulator,15 for a third order modulator, and 19 for a fourth order modulator. The maximum phase detector frequency given the electrical specifications, modulator order, and VCO frequency is shown below.

Equation 11. fPD ≤ Min( 104 MHz, fVCO / NMin)

9.6.1.10.3 PLL_NUM[21:0] -- Fractional Numerator

The fractional numerator is formed by the NUM word that is split between two registers and applies in fractional mode only. The fractional numerator, PLL_NUM must be less than or equal to the fractional denominator, PLL_DEN.

FRACTIONAL
NUMERATOR
PLL_NUM[21:16] PLL_NUM[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
...
4194303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1