SNAS824B October   2021  – June 2022 LMX2571-EP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differences Between the LMX2571 and LMX2571-EP
      2. 7.3.2  Reference Oscillator Input
      3. 7.3.3  R-Dividers and Multiplier
      4. 7.3.4  PLL Phase Detector and Charge Pump
        1. 7.3.4.1 CPout Pin Charge Pump Current
        2. 7.3.4.2 Charge Pump Current When Using External VCO
      5. 7.3.5  PLL N-Divider and Fractional Circuitry
      6. 7.3.6  Partially Integrated Loop Filter
      7. 7.3.7  Low-Noise, Fully Integrated VCO
      8. 7.3.8  External VCO Support
      9. 7.3.9  Programmable RF Output Divider
      10. 7.3.10 Programmable RF Output Buffer
      11. 7.3.11 Integrated TX, RX Switch
      12. 7.3.12 Power Down
      13. 7.3.13 Lock Detect
      14. 7.3.14 FSK Modulation
      15. 7.3.15 FastLock
      16. 7.3.16 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Duplex Mode
      3. 7.4.3 FSK Mode
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1  R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2  R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3  R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4  R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5  R46 Register (offset = 2Eh) [reset = 1Ah]
      6. 7.6.6  R42 Register (offset = 2Ah) [reset = 210h]
      7. 7.6.7  R41 Register (offset = 29h) [reset = 810h]
      8. 7.6.8  R40 Register (offset = 28h) [reset = 101Ch]
      9. 7.6.9  R39 Register (offset = 27h) [reset = 11F0h]
      10. 7.6.10 R35 Register (offset = 23h) [reset = 647h]
      11. 7.6.11 R34 Register (offset = 22h) [reset = 1000h]
      12. 7.6.12 R33 Register (offset = 21h) [reset = 0h]
      13. 7.6.13 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      14. 7.6.14 R24 Register (offset = 18h) [reset = 10h]
      15. 7.6.15 R23 Register (offset = 17h) [reset = 10A4h]
      16. 7.6.16 R22 Register (offset = 16h) [reset = 8584h]
      17. 7.6.17 R21 Register (offset = 15h) [reset = 101h]
      18. 7.6.18 R20 Register (offset = 14h) [reset = 28h]
      19. 7.6.19 R19 Register (offset = 13h) [reset = 0h]
      20. 7.6.20 R18 Register (offset = 12h) [reset = 0h]
      21. 7.6.21 R17 Register (offset = 11h) [reset = 0h]
      22. 7.6.22 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      23. 7.6.23 R8 Register (offset = 8h) [reset = 10h]
      24. 7.6.24 R7 Register (offset = 7h) [reset = 10A4h]
      25. 7.6.25 R6 Register (offset = 6h) [reset = 8584h]
      26. 7.6.26 R5 Register (offset = 5h) [reset = 101h]
      27. 7.6.27 R4 Register (offset = 4h) [reset = 28h]
      28. 7.6.28 R3 Register (offset = 3h) [reset = 0h]
      29. 7.6.29 R2 Register (offset = 2h) [reset = 0h]
      30. 7.6.30 R1 Register (offset = 1h) [reset = 0h]
      31. 7.6.31 R0 Register (offset = 0h) [reset = 3h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Direct Digital FSK Modulation
      2. 8.1.2  Frequency and Output Port Switching
      3. 8.1.3  OSCin Configuration
      4. 8.1.4  Register R0 F1F2_INIT, F1F2_MODE Usage
      5. 8.1.5  FastLock With External VCO
      6. 8.1.6  OSCin Slew Rate
      7. 8.1.7  RF Output Buffer Power Control
      8. 8.1.8  RF Output Buffer Type
      9. 8.1.9  MULT Multiplier
      10. 8.1.10 Integrated VCO
    2. 8.2 Typical Applications
      1. 8.2.1 Synthesizer Duplex Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Synthesizer Duplex Mode Application Curves
      2. 8.2.2 PLL Duplex Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 PLL Duplex Mode Application Curves
      3. 8.2.3 Synthesizer/PLL Duplex Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RHH Package36-Pin VQFNTop View
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
Bypass12BypassPlace a 100-nF capacitor to GND.
Bypass23BypassPlace a 100-nF capacitor to GND.
CE19InputChip Enable input. Active HIGH powers on the device.
CLK11InputMICROWIRE clock input.
CPout25OutputInternal VCO charge pump access point to connect to a 2nd order loop filter.
CPoutExt30Output5-V charge pump output used in PLL mode (external VCO).
DAP

GND

GNDThe DAP should be grounded.
DATA12InputMICROWIRE serial data input.
Fin24InputHigh-frequency, AC-coupled input pin for an external VCO. Leave it open or AC-coupled to GND if not being used.
FSK_D07InputFSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).
FSK_D16InputFSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).
FSK_D25InputFSK data bit 2 (FSK PIN mode).
FSK_DV4InputFSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).
FLout129OutputFastLock output control 1 for external switch. Output is HIGH when F1 is selected.
FLout228OutputFastLock output control 2 for external switch. Output is HIGH when F2 is selected.
GND23GNDVCO ground.
GND31GNDCharge pump ground.
GND35GNDOSCin ground.
LE13InputMICROWIRE latch enable input.
MUXout10OutputMultiplexed output that can be assigned to lock detect or readback serial data output.
NC14, 26NCLeave floating, do not connect to GND or power supply.
OSCin34InputReference clock input.
NC8,18, 36NCThese pins may be left floating or connected to GND.
RFoutRx16OutputRF output used to drive receive mixer. Selectable open-drain or push-pull output.
RFoutTx17OutputRF output used to drive transmit signal. Selectable open-drain or push-pull output.
Vcc3p31, 9, 20, 27SupplyConnect to 3.3-V supply.
VccIO15, 33SupplySupply for digital logic interface. Connect to 3.3-V supply.
VcpExt32SupplySupply for 5-V charge pump. Connect to 5-V supply in PLL mode. Connect to either 3.3-V or 5-V supply in synthesizer mode.
VrefVCO22BypassLDO output. Place a 100-nF capacitor to GND.
VregVCO21BypassBias circuitry for the VCO. Place a 2.2-µF capacitor to GND.