SLVSAW6G June   2011  – April 2024 LP2951-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ERROR Function
      2. 6.3.2 Programming Output Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Input Capacitor (CIN)
        2. 7.2.1.2 Output Capacitor (COUT)
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitance Value
        2. 7.2.2.2 Capacitor Types
        3. 7.2.2.3 CBYPASS: Noise and Stability Improvement
        4. 7.2.2.4 ESR Range
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.2.3 CBYPASS: Noise and Stability Improvement

In the LP2951-Q1, an external FEEDBACK pin directly connected to the error amplifier noninverting input can allow stray capacitance to cause instability by shunting the error amplifier feedback to GND, especially at high frequencies. This instability is worsened if high-value external resistors are used to set the output voltage, because a high resistance allows the stray capacitance to play a more significant role (that is, a larger RC time delay is introduced between the output of the error amplifier and the FEEDBACK input, leading to more phase shift and lower phase margin). A solution is to add a 100-pF bypass capacitor (CBYPASS) between OUTPUT and FEEDBACK; because CBYPASS is in parallel with R1, this capacitor lowers the impedance introduced at FEEDBACK at high frequencies, in effect offsetting the effect of the parasitic capacitance by providing more feedback at higher frequencies. More feedback forces the error amplifier to work at a lower loop gain, so COUT must be increased to a minimum of 3.3 μF to improve the regulator phase margin.

CBYPASS can be also used to reduce output noise in the LP2951-Q1. This bypass capacitor reduces the closed-loop gain of the error amplifier at the high frequency, so noise no longer scales with the output voltage. This improvement is more noticeable with higher output voltages, where loop-gain reduction is greatest. An acceptable CBYPASS is calculated as shown in Equation 2:

Equation 2. GUID-3ED9238C-7F87-4E03-87FD-7430052BEF8A-low.gif