SNVS185F February   2002  – April 2017 LP3982

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 No-Load Stability
      2. 7.3.2 Fast Start-Up
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setting (ADJ Version Only)
        3. 8.2.2.3 Output Capacitance
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Noise Bypass Capacitor
        6. 8.2.2.6 Fault Detection
        7. 8.2.2.7 Power Dissipation
        8. 8.2.2.8 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 WSON Mounting
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The LP3982 is package, pin, and performance compatible with Maxim's MAX8860, excluding reverse battery protection and dual-mode function (fixed and adjustable combined).

A 1.25-V bandgap reference, an error amplifier, and a PMOS pass transistor perform voltage regulation while being supported by shutdown, fault, and the usual temperature and current protection circuitry (see Functional Block Diagram).

The regulator topology is the classic type with negative feedback from the output to one of the inputs of the error amplifier. Feedback resistors R1 and R2 are either internal or external to the device, depending on whether it is the fixed-voltage version or the adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of the error amplifier to be virtually equal in voltage. If the output voltage changes due to load changes, the error amplifier provides the appropriate drive to the pass transistor to maintain the error amplifier's inputs as virtually equal. In short, the error amplifier keeps the output voltage constant in order to keep its inputs equal.

7.2 Functional Block Diagram

LP3982 20036913.gif

7.3 Feature Description

7.3.1 No-Load Stability

The LP3982 remains stable during no-load conditions, a necessary feature for CMOS RAM keep-alive applications.

7.3.2 Fast Start-Up

The LP3982 provides fast start-up time for better system efficiency. The start-up speed is maintained when using the optional noise bypass capacitor. An internal 500-μA current source charges the capacitor until it reaches about 90% of its final value.

7.4 Device Functional Modes

7.4.1 Shutdown

The LP3982 goes into sleep mode when the SHDN pin is in a logic low condition. During this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 1 nA typical. The maximum voltage for a logic low at the SHDN pin is 0.4 V. A minimum voltage of 2 V at the SHDN pin turns the LP3982 back on. The SHDN pin may be directly tied to VIN to keep the part on. The SHDN pin may exceed VIN but not the maximum of 6.5 V.

Figure 13 shows an application that uses the SHDN pin. It detects when the battery is too low and disconnects the load by turning off the regulator. A micropower comparator (LMC7215) and reference (LM385) are combined with resistors to set the minimum battery voltage. At the minimum battery voltage, the comparator output goes low and tuns off the LP3982 and corresponding load. Hysteresis is added to the minimum battery threshold to prevent the battery's recovery voltage from falsely indicating an above minimum condition. When the load is disconnected from the battery, it automatically increases in terminal voltage because of the reduced IR drop across its internal resistance. The minimum battery detector of Figure 13 has a low detection threshold (VLT) of 3.6 V that corresponds to the minimum battery voltage. The upper threshold (VUT) is set for 4.6 V to exceed the recovery voltage of the battery.

LP3982 20036902.gif Figure 13. Minimum Battery Detector that Disconnects the Load Via the SHDN Pin of the LP3982

Resistor value for VUT and VLT are determined as follows:

Equation 1. LP3982 20036923.gif

(The application of Figure 13 used a GT of 5 μ mho.)

Equation 2. LP3982 20036924.gif
Equation 3. LP3982 20036925.gif
Equation 4. LP3982 20036926.gif

The above procedure assumes a rail-to-rail output comparator. Essentially, R2 is in parallel with R1 prior to reaching the lower threshold, then R2 becomes parallel with R3 for the upper threshold. Note that the application requires rail-to-rail input as well.

The resistor values shown in Figure 13 are the closest practical to calculated values.