8.3.1.1 Operation

The boost DC-DC converter generates a 7-V to 28-V boost output voltage from a 2.7-V to 5.5-V boost input voltage.

The converter is a magnetic switching PWM mode DC-DC inductive boost converter with a current limit. It uses current programmed mode control, where the inductor current is measured and controlled with the feedback. During start-up, the soft-start function reduces the peak inductor current. Figure 20 shows the boost block diagram.

Figure 20. Boost Circuit Block Diagram

8.3.1.2 Adaptive Boost Output Voltage Control

The boost converter operates in adaptive boost control mode. In this mode, the voltage at the LED pins is monitored by the control loop. It raises the boost voltage when the measured voltage of ANY of the LED strings falls below the voltage threshold of its corresponding LOW comparator. If the headrooms of ALL of the LED strings are above the voltage threshold of their corresponding MID comparator, then the boost voltage is lowered.

Figure 21. Adaptive Headroom Detail

8.3.2.1 PWM Input Duty Measurement

When using PWM input for brightness control the input PWM duty cycle is measured as described in following diagram and the brightness is controlled based on the result. When changing the brightness it must be noted that the measurement cycle is from rising edge to next rising edge and brightness change must be done accordingly (time from rising to rising edge is constant (=cycle time) and falling edge defines the brightness).

Figure 22. PWM Input Duty Cycle Measurement

8.3.2.2 BRTMODE = 00b

With BRTMODE = 00b, the LED output current is controlled by the PWM input duty cycle. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate a PWM-based brightness code. Before the output is generated, the code goes through the curve shaper block. Then the code goes into the hybrid PWM & I Dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current and/or up to 6 PWM output signals.

Figure 23. Brightness Data Path for BRTMODE = 00b

Figure 24. Typical Application Circuit for Devices Configured With BRTMODE = 00

8.3.2.3 BRTMODE = 01b

With BRTMODE = 01b, the LED output current is controlled by the BRTHI/BRTLO registers. Before the output is generated the BRTHI/BRTLO registers-based brightness code goes through the Curve Shaper block. Then the code goes into the hybrid PWM & I dimming block which determines the range of the PWM and current control. The outcome of the Hybrid PWM&I Dimming block is Current and/or up to 6 PWM output signals.

Figure 25. Brightness Data Path for BRTMODE = 01b

8.3.2.4 BRTMODE = 10b

With BRTMODE = 10b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based brightness code. Before the code is multiplied with the BRTHI/BRTLO registers-based brightness code, it goes through the curve shaper block. After the multiplication, the resulting code goes into the hybrid PWM & I dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current or up to 6 PWM output signals.

Figure 26. Brightness Data Path for BRTMODE = 10b

8.3.2.5 BRTMODE = 11b

With BRTMODE = 11b, the LED output current is controlled by the PWM input duty cycle and the BRTHI/BRTLO registers. The PWM detector block measures the duty cycle at the PWM pin and uses it to generate PWM-based brightness code. In this mode, the BRTHI/BRTLO registers-based brightness code goes through the curve shaper block before it is multiplied with the PWM input duty cycle-based brightness code. After the multiplication, the resulting code goes into the hybrid PWM & I dimming block which determines the range of the PWM and Current control. The outcome of the hybrid PWM & I dimming block is current and/or up to 6 PWM output signals.

Figure 27. Brightness Data Path for BRTMODE = 11b

Figure 28. Typical Application Circuit for Devices Configured With BRTMODE = 01, 10, or 11

8.3.2.6 Hybrid PWM & I Dimming Control

Hybrid PWM & I dimming control combines PWM dimming and LED current-dimming control methods. With this dimming control, better optical efficiency is possible from the LEDs compared to pure PWM control while still achieving smooth and accurate control and low brightness levels. The switch point from current-to-PWM control can be set to get the optimal compromise between good matching of the LEDs brightness/white point at low brightness and good optical efficiency.

Figure 29. Dimming Methods

8.3.2.7 Phase Shift PWM Scheme

The phase shift PWM (PSPWM) scheme allows delay of the time when each LED current sink is active. When the LED current sinks are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors to be used. Reduced ripple also reduces the output ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on the boost output by up to six times, therefore transferring the possible audible noise to the frequencies outside the audible range.

The phase difference between each active driver is automatically determined as 360°/number of active drivers.

Figure 30. Phase Shift PWM Dimming Scheme Diagram

8.3.6.1 LED Short Detection

Voltages at the individual current sinks are constantly monitored for the LED SHORT fault. This fault may occur when some LEDs in a string are electrically bypassed making that LED string shorter than the other LED strings. The reduced forward voltage causes the current sink attached to that string to have a higher headroom voltage than the other current sinks. When the headroom voltage is higher than the fault comparator threshold (configured with the 0V field in the LEDEN register), that current sink is disabled, and the PWM phasing is automatically adjusted. The fault comparator threshold is at 2 V, typical.

8.3.6.2 LED OPEN* Detection

When the auto-detect function is disabled, each current sink is also monitored for the LED OPEN* condition. The condition is set when the headroom voltage on one or more current sinks is below the LOW comparator threshold, and the boost voltage is at the maximum. This fault condition may be caused by one or more OPEN LED strings or by one or more current sinks shorted to GND. The LP8557I immediately shuts down the backlight whenever an LED OPEN* condition is detected on any enabled LED drivers. The backlight does not turn on again (regardless of the COMMAND.ON bit) until the STATUS register is read.

8.3.6.3 Undervoltage Detection

The device continuously monitors the voltage on the VDD pin. When the VDD voltage drops below 2.5 V the backlight is immediately shut down, and the UVLO bit is set in the STATUS register. The backlight automatically starts again when the voltage has increased above 2.5 V + 50 mV hysteresis. Hysteresis is implemented to avoid continuously triggering undervoltage.

8.3.6.4 Thermal Shutdown

If the internal temperature reaches 150°C, the deviceimmediately shuts down the backlight to protect it from damage. The TSD bit is also set in the STATUS register. The device re-activates the backlight again when the internal temperature drops below 130°C.

8.3.6.5 Boost Overcurrent Protection

The device automatically limits boost current to 2.4 A . When the 2.4-A limit is reached the BST_OCP bit is set in the STATUS register. It is normal for the device to trigger the boost current limit during the start-up or sudden brightness changes. The STATUS register can be cleared by reading the bit. If the bit is permanently set, it may indicate an issue in the application.

8.3.6.6 Boost Overvoltage Protection

The device automatically limits boost voltage to VBOOST_MAX + 1.6 V. When the limit is reached the BST_OVP bit is set in the STATUS register. It is normal for the device to trigger the boost OVP limit during the start-up or sudden brightness changes. The status register can be cleared by reading the bit. If the bit is permanently set, it may indicate an issue in the application.

8.3.6.7 Boost Undervoltage Protection

The device can detect when the boost voltage is below VBOOST – 2.5 V for longer than 6 ms. When the threshold is reached the BST_UV bit is set in the STATUS register.

8.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bi-directional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). These lines must be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

The default 7-bit I²C address for the LP8557I slave is 2Ch.

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the I²C session (see Figure 33). A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP conditions. The I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I²C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW.

Figure 33. Start And Stop Conditions

After the START condition, the I²C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE, and R/W = 1 indicates a READ. The second byte following the chip address selects the register address to which the data is written. The third byte contains the data for the selected register.

8.5.1.3 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 34. Bit Transfer

Each data transaction is composed of a START Condition, a number of byte transfers (set by the software) and a STOP Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

8.5.1.4 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

Figure 35. Bus Acknowledge Cycle

8.5.1.5 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

8.5.1.6 Control Register Write Cycle

• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master sends further data bytes the control register address is incremented by one after acknowledge signal.
• Write cycle ends when the master creates stop condition.

8.5.1.7 Control Register Read Cycle

• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition.

<> Data from master; [] Data from slave

8.5.1.8 Register Read and Write Detail

Figure 36. Register Write Format

Figure 37. Register Read Format

8.6.1.1 COMMAND

Address: 0x00h

Reset: 0x00h (LP8557I)

8.6.1.2 STATUS

Address: 0x01h

Reset: 0x00h

8.6.1.3 BRTLO

Address: 0x03h

Reset: 0x00h

8.6.1.4 BRTHI

Address: 0x04h

Reset: 0x00h

The brightness level can be updated via one (8 bits) or two (16 bits) register writes. The internal brightness level is 12 bits wide and is only updated when the BRTHI register is written. If the BRTHI register is written without a previous write to the BRTLO register, then the lower order bits of the internal brightness is synthesized from the BRTHI register value.

8.6.1.5 CONFIG

Address: 0x10h

Reset: 0x07h (LP8557I)

The AUTO bit is set, and the LED string configuration is done automatically. The LP8557I allows users to disable the auto-detect function by setting AUTO bit to 0b.

8.6.1.6 CURRENT

Address: 0x11h

Reset: 0x07h (LP8557I)

The ISET bit determines how the maximum LED current is set. On the LP8557I (ISET = 0), the maximum LED current is 25 mA. It may be re-configured via the I²C interface by overriding MAXCURR bits. Note that re-configuration must be done every time the power on VDD pin is recycled.

8.6.1.7 PGEN

Address: 0x12h

Reset: 0x29h (LP8557I)

The PFSET bit distinguishes how the PWM dimming frequency is set. On the LP8557I (PFSET = 0), the PWM dimming frequency is 9.8 kHz by default. It may be re-configured via I²C interface by overriding PFREQ bits. Note that re-configuration must be done every time the power on VDD pin is recycled.

8.6.1.8 BOOST

Address: 0x13h

Reset: 0x02h (LP8557I)

The BFSET bit distinguishes how the boost switching frequency is set. If BFSET = 0, the boost switching frequency is set by the BFREQ bit. If BFSET = 1, the switching frequency is set with an external resistor. On the LP8557I (BFSET = 0), the boost switching frequency is 500 kHz by default. It may be re-configured via the I²C interface by overriding the BFREQ bit. Please note the re-configuration must be done every time the power on the VDD pin is recycled.

The BCSET bit distinguishes how the boost inductor and compensation is set. If BCSET = 0, the boost inductor and compensation is set by the BCOMP bit. If BCSET = 1, the boost inductor and compensation is set with an external resistor. On the LP8557I (BCSET = 0), the boost compensation is set to option 1 by default. It may be re-configured via I²C interface by overriding BCOMP bit. Please note the re-configuration must be done every time the power on the VDD pin is recycled.

8.6.1.9 LEDEN

Address: 0x14h

Reset: 0xBFh (LP8557I)

The ENABLE field configures the strings if the AUTO bit is 0. The LP8557I allows re-configuration of the ENABLE bits via I²C writes. Note that re-configuration must be done every time the power on the VDD pin is recycled.

8.6.1.10 STEP

Address: 0x15h

Reset: 0x00h (LP8557I)

On LP8557I, it is possible to enable slope and advanced slope functions by re-configuration of the STEP and SMOOTH bits appropriately via I²C writes. Note that re-configuration must be done every time power on the VDD pin is recycled.

The STEP field controls the rate of brightness level changes (slope function). Brightness transitions have a fixed step time. The time required to complete a ramp between two levels also depends upon the difference between the starting and ending current levels. For example, when STEP is set to 10b a brightness transition from 0% to 100% takes 100 ms, while a transition from 50% to 100% takes 50 ms.

The SMOOTH field controls the digital smoothing filter (advanced slope function). This filter behaves much like an RC filter. It can be used to remove the overshoot that appears to occur on large brightness changes. The actual amount of smoothing is tailored for the STEP field setting. For example, medium filter strength is higher for 100-ms ramp times than for 50-ms ramp times. This gives 16 possible brightness-level ramping configurations.