SNVSA05A December   2019  – August 2021 LP875701-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Multiphase Switcher Configurations
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.       53
        2. 7.6.1.1  DEV_REV
        3. 7.6.1.2  OTP_REV
        4. 7.6.1.3  BUCK0_CTRL1
        5. 7.6.1.4  BUCK0_DELAY
        6. 7.6.1.5  GPIO2_DELAY
        7. 7.6.1.6  GPIO3_DELAY
        8. 7.6.1.7  RESET
        9. 7.6.1.8  CONFIG
        10. 7.6.1.9  INT_TOP1
        11. 7.6.1.10 INT_TOP2
        12. 7.6.1.11 INT_BUCK_0_1
        13. 7.6.1.12 INT_BUCK_2_3
        14. 7.6.1.13 TOP_STAT
        15. 7.6.1.14 BUCK_0_1_STAT
        16. 7.6.1.15 BUCK_2_3_STAT
        17. 7.6.1.16 TOP_MASK1
        18. 7.6.1.17 TOP_MASK2
        19. 7.6.1.18 BUCK_0_1_MASK
        20. 7.6.1.19 BUCK_2_3_MASK
        21. 7.6.1.20 SEL_I_LOAD
        22. 7.6.1.21 I_LOAD_2
        23. 7.6.1.22 I_LOAD_1
        24. 7.6.1.23 PGOOD_CTRL1
        25. 7.6.1.24 PGOOD_CTRL2
        26. 7.6.1.25 PGOOD_FLT
        27. 7.6.1.26 PLL_CTRL
        28. 7.6.1.27 PIN_FUNCTION
        29. 7.6.1.28 GPIO_CONFIG
        30. 7.6.1.29 GPIO_IN
        31. 7.6.1.30 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Diagnosis and Protection Features

The LP875701-Q1 is capable of providing four levels of protection features:

  • Information of valid regulator output voltage which sets interrupt or PGOOD signal;
  • Warnings for diagnosis which sets interrupt;
  • Protection events which are disabling the regulators affected; and
  • Faults which are causing the device to shutdown.

The LP875701-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next start-up.

Table 7-5 Summary of Interrupt Signals
EVENTRESULTINTERRUPT REGISTER AND BITINTERRUPT MASKSTATUS BITRECOVERY/INTERRUPT CLEAR
Current limit triggered (20-µs debounce)InterruptINT_BUCKx = 1
BUCKx_ILIM_INT = 1		BUCKx_ILIM_MASKBUCKx_ILIM_STATWrite 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current limit is active
Short circuit (VVOUT < 0.35 V at 1 ms after enable) or overload (VVOUT decreasing below 0.35 V during operation, 1 ms debounce)Regulator disable and interruptINT_BUCKx = 1
BUCKx_SC_INT = 1		N/AN/AWrite 1 to BUCKx_SC_INT bit
Thermal warningInterruptTDIE_WARN = 1TDIE_WARN_MASKTDIE_WARN_STATWrite 1 to TDIE_WARN bit
Interrupt is not cleared if temperature is above thermal warning level
Thermal shutdownAll regulators disabled and Output GPIOx set to low and interruptTDIE_SD = 1N/ATDIE_SD_STATWrite 1 to TDIE_SD bit
Interrupt is not cleared if temperature is above thermal shutdown level
VANA overvoltage (VANAOVP)All regulators disabled and Output GPIOx set to low and interruptINT_OVPN/AOVP_STATWrite 1 to INT_OVP bit
Interrupt is not cleared if VANA voltage is above VANA OVP level
Power Good, output voltage reaches the programmed valueInterruptINT_BUCKx = 1
BUCKx_PG_INT = 1		BUCKx_PG_MASKBUCKx_PG_STATWrite 1 to BUCKx_PG_INT bit
GPIOInterruptINT_GPIOGPIO_MASKGPIO_IN registerWrite 1 to INT_GPIO bit
External clock appears or disappearsInterruptNO_SYNC_CLK(1)SYNC_CLK_MASKSYNC_CLK_STATWrite 1 to NO_SYNC_CLK bit
Load current measurement readyInterruptI_LOAD_READY = 1I_LOAD_READY_MASKN/AWrite 1 to I_LOAD_READY bit
Start-Up (NRST rising edge)Device ready for operation, registers reset to default values and interruptRESET_REG = 1RESET_REG_MASKN/AWrite 1 to RESET_REG bit
Glitch on supply voltage and UVLO triggered (VANA falling and rising)Immediate shutdown followed by power up, registers reset to default values and interruptRESET_REG = 1RESET_REG_MASKN/AWrite 1 to RESET_REG bit
Software requested resetImmediate shutdown followed by power up, registers reset to default values and interruptRESET_REG = 1RESET_REG_MASKN/AWrite 1 to RESET_REG bit
(1) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.