SNOS413E August   2000  – November 2016 LPV321-N , LPV324-N , LPV358-N

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics - 2.7 V
    6. 6.6 AC Electrical Characteristics - 2.7 V
    7. 6.7 DC Electrical Characteristics - 5 V
    8. 6.8 AC Electrical Characteristics - 5 V
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Size
      2. 7.3.2 Signal Integrity
      3. 7.3.3 Simplified Board Layout
      4. 7.3.4 Low Supply Current
      5. 7.3.5 Low Supply Voltage
      6. 7.3.6 Rail-to-Rail Output
      7. 7.3.7 Input Includes Ground
    4. 7.4 Device Functional Modes
      1. 7.4.1 Capacitive Load Tolerance
      2. 7.4.2 Input Bias Current Cancellation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Simple Low-Pass Active Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Difference Amplifier
      3. 8.2.3 Instrumentation Circuits
        1. 8.2.3.1 Three Operating Amplifier Instrumentation
        2. 8.2.3.2 Two Operating Amplifier Instrumentation
        3. 8.2.3.3 Single-Supply Inverting Amplifier
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

For best operational performance, use good PCB layout practices including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
  • Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques (SLOA089).
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Figure 47.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

Layout Example

LPV321-N LPV324-N LPV358-N 100060b4.gif Figure 47. Operational Amplifier Board Layout for Noninverting Configuration