SLAS380F April   2004  – March 2022 MSP430FG437 , MSP430FG438 , MSP430FG439

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Supply Current Into AVCC + DVCC Excluding External Current
    5. 8.5  Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
    6. 8.6  Inputs Px.y, TAx, TBx
    7. 8.7  Leakage Current – Ports P1 to P6
    8. 8.8  Outputs – Ports P1 to P6
    9. 8.9  Output Frequency
    10. 8.10 Typical Characteristics – Outputs
    11. 8.11 Wake-Up From LPM3
    12. 8.12 RAM
    13. 8.13 LCD
    14. 8.14 Comparator_A
    15. 8.15 Comparator_A Typical Characteristics
    16. 8.16 Power-On Reset (POR) and Brownout Reset (BOR)
    17. 8.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
    18. 8.18 DCO
    19. 8.19 Crystal Oscillator, XT1 Oscillator
    20. 8.20 Crystal Oscillator, XT2 Oscillator
    21. 8.21 USART0
    22. 8.22 12-Bit ADC, Power Supply and Input Range Conditions
    23. 8.23 12-Bit ADC, External Reference
    24. 8.24 12-Bit ADC, Built-In Reference
    25. 8.25 12-Bit ADC, Timing Parameters
    26. 8.26 12-Bit ADC, Linearity Parameters
    27. 8.27 12-Bit ADC, Temperature Sensor and Built-In VMID
    28. 8.28 12-Bit DAC, Supply Specifications
    29. 8.29 12-Bit DAC, Linearity Specifications
    30. 8.30 12-Bit DAC, Output Specifications
    31. 8.31 12-Bit DAC, Reference Input Specifications
    32. 8.32 12-Bit DAC, Dynamic Specifications
    33. 8.33 12-Bit DAC, Dynamic Specifications (Continued)
    34. 8.34 Operational Amplifier (OA), Supply Specifications
    35. 8.35 Operational Amplifier (OA), Input/Output Specifications
    36. 8.36 Operational Amplifier (OA), Dynamic Specifications
    37. 8.37 OA Dynamic Specifications Typical Characteristics
    38. 8.38 Flash Memory
    39. 8.39 JTAG Interface
    40. 8.40 JTAG Fuse
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Instruction Set
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Special Function Registers (SFRs)
      1. 9.5.1 Interrupt Enable Registers 1 and 2
      2. 9.5.2 Interrupt Flag Registers 1 and 2
      3. 9.5.3 Module Enable Registers 1 and 2
    6. 9.6  Memory Organization
    7. 9.7  Bootstrap Loader (BSL)
    8. 9.8  Flash Memory
    9. 9.9  Peripherals
      1. 9.9.1  DMA Controller
      2. 9.9.2  Oscillator and System Clock
      3. 9.9.3  Brownout, Supply Voltage Supervisor
      4. 9.9.4  Digital I/O
      5. 9.9.5  Basic Timer1
      6. 9.9.6  LCD Drive
      7. 9.9.7  OA
      8. 9.9.8  Watchdog Timer (WDT)
      9. 9.9.9  USART0
      10. 9.9.10 Timer_A3
      11. 9.9.11 Timer_B3
      12. 9.9.12 Comparator_A
      13. 9.9.13 ADC12
      14. 9.9.14 DAC12
      15. 9.9.15 Peripheral File Map
    10. 9.10 Input/Output Schematics
      1. 9.10.1  Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
      2. 9.10.2  Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
      3. 9.10.3  Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
      4. 9.10.4  Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
      5. 9.10.5  Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
      6. 9.10.6  Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
      7. 9.10.7  Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
      8. 9.10.8  Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
      9. 9.10.9  Port P4, P4.6, Input/Output With Schmitt Trigger
      10. 9.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
      11. 9.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
      12. 9.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
      13. 9.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
      14. 9.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
      15. 9.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
      16. 9.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
      17. 9.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
      18. 9.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
      19. 9.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
      20. 9.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
      21. 9.10.21 VeREF+/DAC0
      22. 9.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
      23. 9.10.23 JTAG Fuse Check Mode
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Development Kit
      2. 10.1.2 Device Nomenclature
    2. 10.2 Documentation Support
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.9.15 Peripheral File Map

Table 9-12 shows peripherals with word-access registers, and Table 9-13 shows peripherals with byte-access registers.

Table 9-12 Peripherals With Word Access
PERIPHERALREGISTER NAMEACRONYMOFFSET
WatchdogWatchdog timer controlWDTCTL0120h
Timer_B3Capture/compare register 2TBCCR20196h
Capture/compare register 1TBCCR10194h
Capture/compare register 0TBCCR00192h
Timer_B registerTBR0190h
Capture/compare control 2TBCCTL20186h
Capture/compare control 1TBCCTL10184h
Capture/compare control 0TBCCTL00182h
Timer_B controlTBCTL0180h
Timer_B interrupt vectorTBIV011Eh
Capture/compare register 2TACCR20176h
Capture/compare register 1TACCR10174h
Capture/compare register 0TACCR00172h
Timer_A3Timer_A registerTAR0170h
Capture/compare control 2TACCTL20166h
Capture/compare control 1TACCTL10164h
Capture/compare control 0TACCTL00162h
Timer_A controlTACTL0160h
Timer_A interrupt vectorTAIV012Eh
FlashFlash control 3FCTL3012Ch
Flash control 2FCTL2012Ah
Flash control 1FCTL10128h
DMADMA module control 0DMACTL00122h
DMA module control 1DMACTL10124h
DMA channel 0 controlDMA0CTL01E0h
DMA channel 0 source addressDMA0SA01E2h
DMA channel 0 destination addressDMA0DA01E4h
DMA channel 0 transfer sizeDMA0SZ01E6h
ADC12
(See also Table 9-13)		Conversion memory 15ADC12MEM15015Eh
Conversion memory 14ADC12MEM14015Ch
Conversion memory 13ADC12MEM13015Ah
Conversion memory 12ADC12MEM120158h
Conversion memory 11ADC12MEM110156h
Conversion memory 10ADC12MEM100154h
Conversion memory 9ADC12MEM90152h
Conversion memory 8ADC12MEM80150h
Conversion memory 7ADC12MEM7014Eh
Conversion memory 6ADC12MEM6014Ch
Conversion memory 5ADC12MEM5014Ah
Conversion memory 4ADC12MEM40148h
Conversion memory 3ADC12MEM30146h
Conversion memory 2ADC12MEM20144h
Conversion memory 1ADC12MEM10142h
Conversion memory 0ADC12MEM00140h
Interrupt-vector-word registerADC12IV01A8h
Interrupt-enable registerADC12IE01A6h
Interrupt-flag registerADC12IFG01A4h
Control register 1ADC12CTL101A2h
Control register 0ADC12CTL001A0h
DAC12DAC12_1 dataDAC12_1DAT01CAh
DAC12_1 controlDAC12_1CTL01C2h
DAC12_0 dataDAC12_0DAT01C8h
DAC12_0 controlDAC12_0CTL01C0h
Table 9-13 Peripherals With Byte Access
PERIPHERALREGISTER NAMEACRONYMOFFSET
OA2Operational Amplifier 2 control register 1OA2CTL10C5h
Operational Amplifier 2 control register 0OA2CTL00C4h
OA1Operational Amplifier 1 control register 1OA1CTL10C3h
Operational Amplifier 1 control register 0OA1CTL00C2h
OA0Operational Amplifier 0 control register 1OA0CTL10C1h
Operational Amplifier 0 control register 0OA0CTL00C0h
LCDLCD memory 20LCDM200A4h
  ⋮  ⋮  ⋮
LCD memory 16LCDM160A0h
LCD memory 15LCDM1509Fh
  ⋮  ⋮  ⋮
LCD memory 1LCDM1091h
LCD control and modeLCDCTL090h
ADC12
(Memory control registers require byte access)		ADC memory-control register 15ADC12MCTL1508Fh
ADC memory-control register 14ADC12MCTL1408Eh
ADC memory-control register 13ADC12MCTL1308Dh
ADC memory-control register 12ADC12MCTL1208Ch
ADC memory-control register 11ADC12MCTL1108Bh
ADC memory-control register 10ADC12MCTL1008Ah
ADC memory-control register 9ADC12MCTL9089h
ADC memory-control register 8ADC12MCTL8088h
ADC memory-control register 7ADC12MCTL7087h
ADC memory-control register 6ADC12MCTL6086h
ADC memory-control register 5ADC12MCTL5085h
ADC memory-control register 4ADC12MCTL4084h
ADC memory-control register 3ADC12MCTL3083h
ADC memory-control register 2ADC12MCTL2082h
ADC memory-control register 1ADC12MCTL1081h
ADC memory-control register 0ADC12MCTL0080h
USART0
(UART or SPI mode)		Transmit bufferU0TXBUF077h
Receive bufferU0RXBUF076h
Baud rateU0BR1075h
Baud rateU0BR0074h
Modulation controlU0MCTL073h
Receive controlU0RCTL072h
Transmit controlU0TCTL071h
USART controlU0CTL070h
Comparator_AComparator_A port disableCAPD05Bh
Comparator_A control 2CACTL205Ah
Comparator_A control 1CACTL1059h
BrownOUT, SVSSVS control register (Reset by brownout signal)SVSCTL056h
FLL+ ClockFLL+ Control 1FLL_CTL1054h
FLL+ Control 0FLL_CTL0053h
System clock frequency controlSCFQCTL052h
System clock frequency integratorSCFI1051h
System clock frequency integratorSCFI0050h
Basic Timer1BT counter 2BTCNT2047h
BT counter 1BTCNT1046h
BT controlBTCTL040h
Port P6Port P6 selectionP6SEL037h
Port P6 directionP6DIR036h
Port P6 outputP6OUT035h
Port P6 inputP6IN034h
Port P5Port P5 selectionP5SEL033h
Port P5 directionP5DIR032h
Port P5 outputP5OUT031h
Port P5 inputP5IN030h
Port P4Port P4 selectionP4SEL01Fh
Port P4 directionP4DIR01Eh
Port P4 outputP4OUT01Dh
Port P4 inputP4IN01Ch
Port P3Port P3 selectionP3SEL01Bh
Port P3 directionP3DIR01Ah
Port P3 outputP3OUT019h
Port P3 inputP3IN018h
Port P2Port P2 selectionP2SEL02Eh
Port P2 interrupt enableP2IE02Dh
Port P2 interrupt-edge selectP2IES02Ch
Port P2 interrupt flagP2IFG02Bh
Port P2 directionP2DIR02Ah
Port P2 outputP2OUT029h
Port P2 inputP2IN028h
Port P1Port P1 selectionP1SEL026h
Port P1 interrupt enableP1IE025h
Port P1 interrupt-edge selectP1IES024h
Port P1 interrupt flagP1IFG023h
Port P1 directionP1DIR022h
Port P1 outputP1OUT021h
Port P1 inputP1IN020h
Special functionsSFR module enable 2ME2005h
SFR module enable 1ME1004h
SFR interrupt flag 2IFG2003h
SFR interrupt flag 1IFG1002h
SFR interrupt enable 2IE2001h
SFR interrupt enable 1IE1000h