SLASEE4C January   2018  – December 2019 MSP430FR2512 , MSP430FR2522

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Types
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1       Absolute Maximum Ratings
    2. 5.2       ESD Ratings
    3. 5.3       Recommended Operating Conditions
    4. 5.4       Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5       Active Mode Supply Current Per MHz
    6. 5.6       Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
    7. 5.7       Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8       Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9       Typical Characteristics - Low-Power Mode Supply Currents
    10. Table 5-1 Typical Characteristics – Current Consumption Per Module
    11. 5.10      Thermal Resistance Characteristics
    12. 5.11      Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. Table 5-2 PMM, SVS and BOR
      2. 5.11.2  Reset Timing
        1. Table 5-3 Wake-up Times From Low-Power Modes and Reset
      3. 5.11.3  Clock Specifications
        1. Table 5-4 XT1 Crystal Oscillator (Low Frequency)
        2. Table 5-5 DCO FLL, Frequency
        3. Table 5-6 DCO Frequency
        4. Table 5-7 REFO
        5. Table 5-8 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. Table 5-9 Module Oscillator (MODOSC)
      4. 5.11.4  Digital I/Os
        1. Table 5-10 Digital Inputs
        2. Table 5-11 Digital Outputs
        3. 5.11.4.1   Typical Characteristics – Outputs at 3 V and 2 V
      5. 5.11.5  VREF+ Built-in Reference
        1. Table 5-12 VREF+
      6. 5.11.6  Timer_A
        1. Table 5-13 Timer_A
      7. 5.11.7  eUSCI
        1. Table 5-14 eUSCI (UART Mode) Clock Frequency
        2. Table 5-15 eUSCI (UART Mode)
        3. Table 5-16 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-17 eUSCI (SPI Master Mode)
        5. Table 5-18 eUSCI (SPI Slave Mode)
        6. Table 5-19 eUSCI (I2C Mode)
      8. 5.11.8  ADC
        1. Table 5-20 ADC, Power Supply and Input Range Conditions
        2. Table 5-21 ADC, 10-Bit Timing Parameters
        3. Table 5-22 ADC, 10-Bit Linearity Parameters
      9. 5.11.9  CapTIvate
        1. Table 5-23 CapTIvate Electrical Characteristics
        2. Table 5-24 CapTIvate Signal-to-Noise Ratio Characteristics
      10. 5.11.10 FRAM
        1. Table 5-25 FRAM
      11. 5.11.11 Debug and Emulation
        1. Table 5-26 JTAG, Spy-Bi-Wire Interface
        2. Table 5-27 JTAG, 4-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Standard Interface
    7. 6.7  Spy-Bi-Wire Interface (SBW)
    8. 6.8  FRAM
    9. 6.9  Memory Protection
    10. 6.10 Peripherals
      1. 6.10.1  Power-Management Module (PMM)
      2. 6.10.2  Clock System (CS) and Clock Distribution
      3. 6.10.3  General-Purpose Input/Output Port (I/O)
      4. 6.10.4  Watchdog Timer (WDT)
      5. 6.10.5  System (SYS) Module
      6. 6.10.6  Cyclic Redundancy Check (CRC)
      7. 6.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 6.10.8  Timers (Timer0_A3, Timer1_A3)
      9. 6.10.9  Hardware Multiplier (MPY)
      10. 6.10.10 Backup Memory (BAKMEM)
      11. 6.10.11 Real-Time Clock (RTC)
      12. 6.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 6.10.13 CapTIvate Technology
      14. 6.10.14 Embedded Emulation Module (EEM)
    11. 6.11 Input/Output Diagrams
      1. 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptors
    13. 6.13 Memory
      1. 6.13.1 Memory Organization
      2. 6.13.2 Peripheral File Map
    14. 6.14 Identification
      1. 6.14.1 Revision Identification
      2. 6.14.2 Device Identification
      3. 6.14.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Layout Guidelines
      2. 7.2.2 CapTIvate Peripheral
        1. 7.2.2.1 Device Connection and Layout Fundamentals
        2. 7.2.2.2 Measurements
          1. 7.2.2.2.1 SNR
          2. 7.2.2.2.2 Sensitivity
          3. 7.2.2.2.3 Power
    3. 7.3 CapTIvate Technology Evaluation
  8. 8Device and Documentation Support
    1. 8.1  Getting Started and Next Steps
    2. 8.2  Device Nomenclature
    3. 8.3  Tools and Software
    4. 8.4  Documentation Support
    5. 8.5  Related Links
    6. 8.6  Community Resources
    7. 8.7  Trademarks
    8. 8.8  Electrostatic Discharge Caution
    9. 8.9  Export Control Notice
    10. 8.10 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • RHL|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

Changes from revision B to revision C

Changes from August 20, 2019 to December 10, 2019

  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 5.3, Recommended Operating ConditionsGo
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 5.3, Recommended Operating ConditionsGo
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Table 5-4, XT1 Crystal Oscillator (Low Frequency)Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Table 5-4, XT1 Crystal Oscillator (Low Frequency)Go
  • Corrected the test conditions for the RI parameter in Table 5-20, ADC, Power Supply and Input Range ConditionsGo
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Table 5-21, ADC, 10-Bit Timing ParametersGo
  • Added "1.5-V reference factor" in Table 6-18, Device DescriptorsGo
  • Changed the CRC covered end address to 0x1AF5 in note (1) in Table 6-18, Device DescriptorsGo

Changes from November 8, 2018 to August 19, 2019

  • Updated Section 1.1, FeaturesGo
  • Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (11) on Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Changed CapTIvate BSWP demonstration board to CapTIvate phone demonstration board in note (19) on Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Moved CREG and CELECTRODE from Section 5.3, Recommended Operating Conditions to Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Added test condition for CELECTRODE in Table 5-23 , CapTIvate Electrical CharacteristicsGo
  • Changed the symbol and description of the DCCAPCLK parameter in Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Moved the SNR parameter to Table 5-24, CapTIvate Signal-to-Noise Ratio CharacteristicsGo
  • Updated Section 7.2.2, CapTIvate PeripheralGo
  • Updated Section 8.2, Device NomenclatureGo

Changes from January 12, 2018 to November 7, 2018

  • Removed "15-cm" from the "Proximity Sensing" item in Section 1.1, FeaturesGo
  • Changed list item "Wide supply voltage range from 3.6 V down to 1.8 V..." in Section 1.1, FeaturesGo
  • Updated Section 3.1, Related ProductsGo
  • Changed HBM limit to ±1000 V and CDM limit to ±250 V in Section 5.2, ESD RatingsGo
  • Changed the MIN value of the VCC parameter from 2 V to 1.8 V in Section 5.3, Recommended Operating ConditionsGo
  • Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in Section 5.7, Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External CurrentGo
  • Changed the crystal in the footnote that begins "Characterized with a Seiko Crystal SC-32S crystal..." in Section 5.8, Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External CurrentGo
  • Added note on VSVSH- and VSVSH+ parameters to Table 5-2, PMM, SVS and BORGo
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fREFO, dfREFO/ dVCC, and fDC parameters and in note (2) in Table 5-7, REFOGo
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the dfVLO/dVCC parameter and in note (2) in Table 5-8, Internal Very-Low-Power Low-Frequency Oscillator (VLO)Go
  • Changed the minimum VCC from 2.0 V to 1.8 V in the test conditions for the fMODOSC/dVCC parameter in Table 5-9, Module Oscillator (MODOSC)Go
  • Added the SNR parameter in Table 5-23, CapTIvate Electrical CharacteristicsGo
  • Corrected bitfield from RTCCLK to RTCCKSEL in table note that starts "Controlled by ..." in Table 6-8, Clock DistributionGo
  • Corrected bitfield from IRDSEL to IRDSSEL in Section 6.10.8, Timers (Timer0_A3, Timer1_A3), in the description that starts "The interconnection of Timer0_A3 and ..."Go
  • Corrected ADCINCHx column heading in Table 6-13, ADC Channel ConnectionsGo
  • Added P1SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h)Go
  • Added P2SELC information in Table 6-28, Port P1, P2 Registers (Base Address: 0200h)Go