SBOSAH7A October   2023  – February 2024 OPA4990-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Function
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Common-Mode Voltage Range
      6. 6.3.6 Phase Reversal Protection
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Slew Rate Limit for Input Protection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Tape and Reel Information
    2. 10.2 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7V to 40V (±1.35V to ±20V) at TA = 25°C, RL = 10kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.3 ±2.1 mV
TA = –40°C to 125°C ±2.26
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.6 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 4V to 40V TA = –40°C to 125°C ±0.1 ±1.3 µV/V
VCM = V–, VS = 2.7V to 40V(1) ±0.75 ±10
Channel separation f = 0Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±5 pA
NOISE
EN Input voltage noise f = 0.1Hz to 10Hz   6 µVPP
  1   µVRMS
eN Input voltage noise density f = 1kHz 30   nV/√Hz
f = 10kHz   28  
iN Input current noise f = 1kHz   2   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 40V, (V–) – 0.1V < VCM < (V+) – 2V (PMOS pair) TA = –40°C to 125°C 97 115 dB
VS = 4V, (V–) – 0.1V < VCM < (V+) – 2V (PMOS pair) 72 90
VS = 2.7V, (V–) – 0.1V < VCM < (V+) – 2V (PMOS pair)(1) 70 90
VS = 2.7 – 40V, (V+) – 1V < VCM < (V+) + 0.1V (NMOS pair) 80
(V+) – 2V < VCM < (V+) – 1V See Offset Voltage (Transition Region) in the Typical Characteristics section
INPUT CAPACITANCE
ZID Differential 540 || 3 GΩ ||pF
ZICM Common-mode 6 || 1 TΩ ||pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 40V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V		 120 145 dB
TA = –40°C to 125°C 142
VS = 4V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V		 104 130
TA = –40°C to 125°C 125
VS = 2.7V, VCM = VS / 2,
(V–) + 0.1V < VO < (V+) –  0.1V(1)		 99 118 dB
TA = –40°C to 125°C 117 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1.1 MHz
SR Slew rate VS = 40V, G = +1, CL = 20pF 4.5 V/μs
tS Settling time To 0.1%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 4 µs
To 0.1%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 2
To 0.01%, VS = 40V, VSTEP = 10V , G = +1, CL = 20pF 5
To 0.01%, VS = 40V, VSTEP = 2V , G = +1, CL = 20pF 3
Phase margin G = +1, RL = 10kΩ, CL = 20pF 60 °
Overload recovery time VIN  × gain > VS 600 ns
THD+N Total harmonic distortion + noise VS = 40V, VO = 1VRMS, G = 1, f = 1kHz 0.00162%
OUTPUT
  Voltage output swing from rail Positive and negative
rail headroom		 VS = 40V, RL = no load   2 mV
VS = 40V, RL = 10kΩ   45 60
VS = 40V, RL = 2kΩ   200 300
VS = 2.7V, RL = no load   1
VS = 2.7V, RL = 10kΩ   5 20
VS = 2.7V, RL = 2kΩ   25 50
ISC Short-circuit current ±80 mA
CLOAD Capacitive load drive See Small-Signal Overshoot vs Capacitive Load in the Typical Characteristics section
ZO Open-loop output impedance f = 1MHz, IO = 0 A 575 Ω
POWER SUPPLY
IQ Quiescent current per amplifier OPA2990-Q1, OPA4990-Q1, IO = 0 A 120 150 µA
TA = –40°C to 125°C 160
OPA990-Q1, IO = 0 A 130 170
TA = –40°C to 125°C 175
Turn-on time At TA = 25°C, VS = 40V, VS ramp rate > 0.3V/µs
 40 μs
(1) Specified by characterization only.