SCPS148I October   2005  – June 2022 PCA9546A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Interrupt and Reset Timing Requirements
    8. 6.8 Switching Characteristics
  7. 7 Parameter Measurement Information
    1.     16
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
        1. 8.4.1.1 RESET Errata
          1.        24
          2.        25
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Control Register
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register Description
      3. 8.6.3 Control Register Definition
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT
VPORR Power-on reset voltage, VCC rising No load, VI = VCC or GND 1.2 1.5 V
VPORF Power-on reset voltage, VCC falling(2) No load, VI = VCC or GND

0.8

1

V
Vpass Switch output voltage VSWin = VCC, ISWout = –100 μA 5 V 3.6 V
4.5 V to 5.5 V 2.6 4.5
3.3 V 1.9
3 V to 3.6 V 1.6 2.8
2.5 V 1.5
2.3 V to 2.7 V 1.1 2
IOL SCL, SDA VOL = 0.4 V 2.3 V to 5.5 V 3 7 mA
VOL = 0.6 V 6 10
II SCL, SDA VI = VCC or GND 2.3 V to 5.5 V ±1 μA
SC3–SC0, SD3–SD0 ±1
A2–A0 ±1
RESET(4) ±1
ICC Operating mode fSCL = 100 kHz VI = VCC or GND, IO = 0 5.5 V 3 12 μA
3.6 V 3 11
2.7 V 3 10
Standby mode Low inputs VI = GND, IO = 0 5.5 V 1.6

2
3.6 V 1

1.3
2.7 V 0.7

1.1
High inputs VI = VCC, IO = 0 5.5 V 1.6

2
3.6 V 1 1.3
2.7 V 0.7

1.1
ΔICC Supply-current change SCL, SDA SCL or SDA input at 0.6 V,
Other inputs at VCC or GND		 8 15 μA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND		 2.3 V to 5.5 V 8 15
Ci A2–A0 VI = VCC or GND 2.3 V to 5.5 V 4.5 6 pF
RESET 4.5 5.5
Cio(OFF)(3) SCL, SDA VI = VCC or GND, Switch OFF 2.3 V to 5.5 V 15 19 pF
SC3–SC0, SD3–SD0 6 8
RON Switch on-state resistance VO = 0.4 V, IO = 15 mA 4.5 V to 5.5 V 4 10 16 Ω
3 V to 3.6 V 5 13 20
VO = 0.4 V, IO = 10 mA 2.3 V to 2.7 V 7 16 45
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(2)

The power-on reset circuit resets the I2C bus logic with VCC < VPORF.

(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
(4) RESET = VCC (held high) when all other input voltages, VI = GND.