7.3.1 Analog Inputs and Outputs

The PGA2310 includes two independent channels, referred to as the left and right channels. Each channel has a corresponding input and output pin. The input and output pins are unbalanced, or referenced to analog ground (either AGNDR or AGNDL). The inputs are V_INR (pin 9) and V_INL (pin 16), while the outputs are V_OUTR (pin 11) and V_OUTL (pin 14).

The input and output pins may swing within 1.5 V of the analog power supplies, V_A+ (pin 12) and V_A− (pin 13). Given V_A+ = 15 V and V_A− = −15 V, the maximum input or output voltage range is 27 V_PP.

Drive the PGA2310 with a low source impedance. If a source impedance of greater than 600 Ω is used, the distortion performance of the PGA2310 begins to degrade.

7.3.2 Serial Control Port

The serial control port is used to program the gain settings for the PGA2310. The serial control port includes three input pins and one output pin. The inputs include CS (pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin is SDO (pin 7).

The CS pin functions as the chip select input. Data may be written to the PGA2310 only when CS is low. SDI is the serial data input pin. Control data is provided as a 16-bit word at the SDI pin, 8 bits each for the left and right channel gain settings. Data is formatted as MSB first, in straight binary code. SCLK is the serial clock input. Data is clocked into SDI on the rising edge of SCLK.

SDO is the serial data output pin, and used when daisy-chaining multiple PGA2310 devices. Daisy-chain operation is described in Daisy-Chaining Multiple PGA2310 Devices. SDO is a tristate output, and assumes a high impedance state when CS is high.

The protocol for the serial control port is shown in Figure 10. Figure 11 shows detailed timing specifications of the serial control port.

Figure 10. Serial Interface Protocol

Figure 11. Serial Interface Timing Requirements

7.3.3 Gain Settings

The gain for each channel is set by its corresponding 8-bit code, either R[7:0] or L[7:0] (see Figure 10). The gain code data is straight binary format. If N equals the decimal equivalent of R[7:0] or L[7:0], then the following relationships exist for the gain settings:

• For N = 0: Mute Condition. The input multiplexer is connected to analog ground (AGNDR or AGNDL).
• For N = 1 to 255: Gain (dB) = 31.5 − [0.5 • (255 − N)]

This results in a gain range of 31.5 dB (with N = 255) to −95.5 dB (with N = 1).

Changes in gain setting may be made with or without zero crossing detection. The operation of the zero crossing detector and time-out circuitry is discussed in Zero Crossing Detection.

7.3.4 Daisy-Chaining Multiple PGA2310 Devices

To reduce the number of control signals required to support multiple PGA2310 devices on a printed-circuit-board, the serial control port supports daisy-chaining of multiple PGA2310 devices. Figure 12 shows the connection requirements for daisy-chain operation. This arrangement allows a three-wire serial interface to control many PGA2310 devices.

Figure 12. Daisy-Chaining Multiple PGA2310 Devices

As shown in Figure 12, the SDO pin from device 1 is connected to the SDI input of device 2, and is repeated for additional devices. This in turn forms a large shift register, in which gain data may be written for all PGA2310s connected to the serial bus. The length of the shift register is 16 × N bits, where N is equal to the number of PGA2310 devices included in the chain. The CS input must remain low for 16 × N SCLK periods, where N is the number of devices connected in the chain, to allow enough SCLK cycles to load all devices.

7.3.5 Zero Crossing Detection

The PGA2310 includes a zero crossing detection function that can provide for noise-free level transitions. The concept is to change gain settings on a zero crossing of the input signal, thus minimizing audible glitches. This function is enabled or disabled using the ZCEN input (pin 1). When ZCEN is low, zero crossing detection is disabled. When ZCEN is high, zero crossing detection is enabled.

The zero crossing detection takes effect with a change in gain setting for a corresponding channel. The new gain setting is not latched until either two zero crossings are detected, or a time-out period of 16 ms has elapsed without detecting two zero crossings. In the case of a time-out, the new gain setting takes effect with no attempt to minimize audible artifacts.

7.3.6 Mute Function

The PGA2310 includes a mute function. This function may be activated by either the MUTE input (pin 8), or by setting the gain byte value for one or both channels to 00_HEX. The MUTE pin may be used to mute both channels, while the gain setting may be used to selectively mute the left and right channels. Muting is accomplished by switching the input multiplexer to analog ground (AGNDR or AGNDL) with zero crossing enabled.

The MUTE pin is active low. When MUTE is low, each channel is muted following the next zero crossing event or time-out that occurs on that channel. If MUTE becomes active while CS is also active, the mute takes effect once the CS pin goes high. When the MUTE pin is high, the PGA2310 operates normally, with the mute function disabled.

7.4.1 Power-Up State

On power up, all internal flip-flops are reset. The gain byte value for both the left and right channels are set to 00_HEX, or mute condition. The gain remains at this setting until the host controller programs new settings for each channel using the serial control port.