SLASEJ4C April 2017 – February 2023 PGA460
PRODUCTION DATA
#GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/REGMAP_TABLE_1 lists the memory-mapped registers for the REGMAP. All register offset addresses not listed in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/REGMAP_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | USER_DATA1 | User general purpose data register 1 | Go |
1h | USER_DATA2 | User general purpose data register 2 | Go |
2h | USER_DATA3 | User general purpose data register 3 | Go |
3h | USER_DATA4 | User general purpose data register 4 | Go |
4h | USER_DATA5 | User general purpose data register 5 | Go |
5h | USER_DATA6 | User general purpose data register 6 | Go |
6h | USER_DATA7 | User general purpose data register 7 | Go |
7h | USER_DATA8 | User general purpose data register 8 | Go |
8h | USER_DATA9 | User general purpose data register 9 | Go |
9h | USER_DATA10 | User general purpose data register 10 | Go |
Ah | USER_DATA11 | User general purpose data register 11 | Go |
Bh | USER_DATA12 | User general purpose data register 12 | Go |
Ch | USER_DATA13 | User general purpose data register 13 | Go |
Dh | USER_DATA14 | User general purpose data register 14 | Go |
Eh | USER_DATA15 | User general purpose data register 15 | Go |
Fh | USER_DATA16 | User general purpose data register 16 | Go |
10h | USER_DATA17 | User general purpose data register 17 | Go |
11h | USER_DATA18 | User general purpose data register 18 | Go |
12h | USER_DATA19 | User general purpose data register 19 | Go |
13h | USER_DATA20 | User general purpose data register 20 | Go |
14h | TVGAIN0 | Time-varying gain map segment configuration register 0 | Go |
15h | TVGAIN1 | Time-varying gain map segment configuration register 1 | Go |
16h | TVGAIN2 | Time-varying gain map segment configuration register 2 | Go |
17h | TVGAIN3 | Time-varying gain map segment configuration register 3 | Go |
18h | TVGAIN4 | Time-varying gain map segment configuration register 4 | Go |
19h | TVGAIN5 | Time-varying gain map segment configuration register 5 | Go |
1Ah | TVGAIN6 | Time-varying gain map segment configuration register 6 | Go |
1Bh | INIT_GAIN | AFE initial gain configuration register | Go |
1Ch | FREQUENCY | Burst frequency configuration register | Go |
1Dh | DEADTIME | Deadtime and threshold deglitch configuration | Go |
1Eh | PULSE_P1 | Preset1 pulse burst, IO control and UART diagnostic configuration | Go |
1Fh | PULSE_P2 | Preset2 pulse burst, IO control and UART diagnostic configuration | Go |
20h | CURR_LIM_P1 | Preset1 driver current limit configuration | Go |
21h | CURR_LIM_P2 | Preset2 current limit and low pass filter configuration | Go |
22h | REC_LENGTH | Echo data record period configuration register | Go |
23h | FREQ_DIAG | Frequency diagnostic configuration register | Go |
24h | SAT_FDIAG_TH | Decay saturation, frequency diag error and Preset1 non-linear control configuration | Go |
25h | FVOLT_DEC | Voltage thresholds and Preset2 non-linear scaling configuration | Go |
26h | DECPL_TEMP | De-couple temp and AFE gain range configuration | Go |
27h | DSP_SCALE | DSP path non-linear scaling and noise level configuration | Go |
28h | TEMP_TRIM | Temperature compensation values register | Go |
29h | P1_GAIN_CTRL | Preset1 digital gain configuration register | Go |
2Ah | P2_GAIN_CTRL | Preset2 digital gain configuration register | Go |
2Bh | EE_CRC | User EEPROM space CRC value register | Go |
40h | EE_CNTRL | User EEPROM control register | Go |
41h | BPF_A2_MSB | BPF A2 coefficient most-significant byte configuration | Go |
42h | BPF_A2_LSB | BPF A2 coefficient least-significant byte configuration | Go |
43h | BPF_A3_MSB | BPF A3 coefficient most-significant byte configuration | Go |
44h | BPF_A3_LSB | BPF A3 coefficient least-significant byte configuration | Go |
45h | BPF_B1_MSB | BPF B1 coefficient most-significant byte configuration | Go |
46h | BPF_B1_LSB | BPF B1 coefficient least-significant byte configuration | Go |
47h | LPF_A2_MSB | LPF A2 coefficient most-significant byte configuration | Go |
48h | LPF_A2_LSB | LPF A2 coefficient least-significant byte configuration | Go |
49h | LPF_B1_MSB | LPF B1 coefficient most-significant byte configuration | Go |
4Ah | LPF_B1_LSB | LPF B1 coefficient least-significant byte configuration | Go |
4Bh | TEST_MUX | Test multiplexer configuration register | Go |
4Ch | DEV_STAT0 | Device Status register 0 | Go |
4Dh | DEV_STAT1 | Device status register 1 | Go |
5Fh | P1_THR_0 | Preset1 threshold map segment configuration register 0 | Go |
60h | P1_THR_1 | Preset1 threshold map segment configuration register 1 | Go |
61h | P1_THR_2 | Preset1 threshold map segment configuration register 2 | Go |
62h | P1_THR_3 | Preset1 threshold map segment configuration register 3 | Go |
63h | P1_THR_4 | Preset1 threshold map segment configuration register 4 | Go |
64h | P1_THR_5 | Preset1 threshold map segment configuration register 5 | Go |
65h | P1_THR_6 | Preset1 threshold map segment configuration register 6 | Go |
66h | P1_THR_7 | Preset1 threshold map segment configuration register 7 | Go |
67h | P1_THR_8 | Preset1 threshold map segment configuration register 8 | Go |
68h | P1_THR_9 | Preset1 threshold map segment configuration register 9 | Go |
69h | P1_THR_10 | Preset1 threshold map segment configuration register 10 | Go |
6Ah | P1_THR_11 | Preset1 threshold map segment configuration register 11 | Go |
6Bh | P1_THR_12 | Preset1 threshold map segment configuration register 12 | Go |
6Ch | P1_THR_13 | Preset1 threshold map segment configuration register 13 | Go |
6Dh | P1_THR_14 | Preset1 threshold map segment configuration register 14 | Go |
6Eh | P1_THR_15 | Preset1 threshold map segment configuration register 15 | Go |
6Fh | P2_THR_0 | Preset2 threshold map segment configuration register 0 | Go |
70h | P2_THR_1 | Preset2 threshold map segment configuration register 1 | Go |
71h | P2_THR_2 | Preset2 threshold map segment configuration register 2 | Go |
72h | P2_THR_3 | Preset2 threshold map segment configuration register 3 | Go |
73h | P2_THR_4 | Preset2 threshold map segment configuration register 4 | Go |
74h | P2_THR_5 | Preset2 threshold map segment configuration register 5 | Go |
75h | P2_THR_6 | Preset2 threshold map segment configuration register 6 | Go |
76h | P2_THR_7 | Preset2 threshold map segment configuration register 7 | Go |
77h | P2_THR_8 | Preset2 threshold map segment configuration register 8 | Go |
78h | P2_THR_9 | Preset2 threshold map segment configuration register 9 | Go |
79h | P2_THR_10 | Preset2 threshold map segment configuration register 10 | Go |
7Ah | P2_THR_11 | Preset2 threshold map segment configuration register 11 | Go |
7Bh | P2_THR_12 | Preset2 threshold map segment configuration register 12 | Go |
7Ch | P2_THR_13 | Preset2 threshold map segment configuration register 13 | Go |
7Dh | P2_THR_14 | Preset2 threshold map segment configuration register 14 | Go |
7Eh | P2_THR_15 | Preset2 threshold map segment configuration register 15 | Go |
7Fh | THR_CRC | Threshold map configuration registers data CRC register | Go |
Complex bit access types are encoded to fit into small table cells. #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/REGMAP_LEGEND shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RC | C R | to Clear Read |
RH | H R | Set or cleared by hardware Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
USER_DATA1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA1_TABLE.
Return to Summary Table.
User general purpose data register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_1 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_1 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA2_TABLE.
Return to Summary Table.
User general purpose data register 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_2 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_2 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA3 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA3_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA3_TABLE.
Return to Summary Table.
User general purpose data register 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_3 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_3 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA4 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA4_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA4_TABLE.
Return to Summary Table.
User general purpose data register 4
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_4 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_4 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA5 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA5_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA5_TABLE.
Return to Summary Table.
User general purpose data register 5
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_5 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_5 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA6 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA6_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA6_TABLE.
Return to Summary Table.
User general purpose data register 6
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_6 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_6 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA7 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA7_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA7_TABLE.
Return to Summary Table.
User general purpose data register 7
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_7 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_7 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA8 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA8_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA8_TABLE.
Return to Summary Table.
User general purpose data register 8
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_8 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_8 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA9 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA9_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA9_TABLE.
Return to Summary Table.
User general purpose data register 9
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_9 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_9 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA10 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA10_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA10_TABLE.
Return to Summary Table.
User general purpose data register 10
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_10 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_10 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA11 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA11_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA11_TABLE.
Return to Summary Table.
User general purpose data register 11
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_11 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_11 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA12 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA12_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA12_TABLE.
Return to Summary Table.
User general purpose data register 12
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_12 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_12 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA13 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA13_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA13_TABLE.
Return to Summary Table.
User general purpose data register 13
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_13 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_13 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA14 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA14_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA14_TABLE.
Return to Summary Table.
User general purpose data register 14
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_14 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_14 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA15 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA15_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA15_TABLE.
Return to Summary Table.
User general purpose data register 15
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_15 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_15 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA16 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA16_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA16_TABLE.
Return to Summary Table.
User general purpose data register 16
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_16 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_16 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA17 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA17_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA17_TABLE.
Return to Summary Table.
User general purpose data register 17
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_17 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_17 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA18 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA18_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA18_TABLE.
Return to Summary Table.
User general purpose data register 18
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_18 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_18 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA19 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA19_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA19_TABLE.
Return to Summary Table.
User general purpose data register 19
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_19 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_19 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
USER_DATA20 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA20_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_USER_DATA20_TABLE.
Return to Summary Table.
User general purpose data register 20
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
USER_20 | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | USER_20 | R/W | 0h | This register has no internal functional use. Register content is User defined solely for external use . |
TVGAIN0 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN0_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN0_TABLE.
Return to Summary Table.
Time-varying gain map segment configuration register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_T0 | TVG_T1 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TVG_T0 | R/W | 0h | Time varying gain Start time parameter: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
3:0 | TVG_T1 | R/W | 0h | Time Varying Gain T0/T1 Delta Time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
TVGAIN1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN1_TABLE.
Return to Summary Table.
Time-varying gain map segment configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_T2 | TVG_T3 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TVG_T2 | R/W | 0h | Time Varying Gain T1/T2 Delta Time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
3:0 | TVG_T3 | R/W | 0h | Time Varying Gain T2/T3 Delta Time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
TVGAIN2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN2_TABLE.
Return to Summary Table.
Time-varying gain map segment configuration register 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_T4 | TVG_T5 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TVG_T4 | R/W | 0h | Time Varying Gain T3/T4 Delta Time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
3:0 | TVG_T5 | R/W | 0h | Time Varying Gain T4/T5 Delta Time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs |
TVGAIN3 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN3_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN3_TABLE.
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Time-varying gain map segment configuration register 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_G1 | TVG_G2 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | TVG_G1 | R/W | 0h | TVG Point 1 Gain Value: Gain = 0.5 × (TVG_G1 +1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
1:0 | TVG_G2 | R/W | 0h | TVG Point 2 Gain Value: Gain = 0.5 × (TVG_G2 + 1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
TVGAIN4 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN4_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN4_TABLE.
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Time-varying gain map segment configuration register 4
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_G2 | TVG_G3 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TVG_G2 | R/W | 0h | TVG Point 2 Gain Value: Gain = 0.5 × (TVG_G2 +1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
3:0 | TVG_G3 | R/W | 0h | TVG Point 3 Gain Value: Gain = 0.5 × (TVG_G3 + 1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
TVGAIN5 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN5_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN5_TABLE.
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Time-varying gain map segment configuration register 5
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_G3 | TVG_G4 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | TVG_G3 | R/W | 0h | TVG Point 3 Gain Value: Gain = 0.5 × (TVG_G3 +1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
5:0 | TVG_G4 | R/W | 0h | TVG Point 4 Gain Value: Gain = 0.5 × (TVG_G4 + 1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
TVGAIN6 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN6_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TVGAIN6_TABLE.
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Time-varying gain map segment configuration register 6
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TVG_G5 | RESERVED | FREQ_SHIFT | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | TVG_G5 | R/W | 0h | TVG Point 5 Gain Value: Gain = 0.5 × (TVG_G5 +1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
1 | RESERVED | R/W | 0h | Reserved |
0 | FREQ_SHIFT | R/W | 0h | Burst Frequency Range Shift: 0b = Disabled 1b = Enabled, active frequency = 6 × frequency result from calculation using equation given in the FREQUENCY register |
INIT_GAIN is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_INIT_GAIN_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_INIT_GAIN_TABLE.
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AFE initial gain configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_BW | GAIN_INIT | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | BPF_BW | R/W | 0h | Digital bandpass filter bandwidth: BandWidth = 2 × (BPF_BW + 1) [kHz] |
5:0 | GAIN_INIT | R/W | 0h | Initial AFE Gain: Init_Gain = 0.5 × (GAIN_INIT+1) + value(AFE_GAIN_RNG) [dB] Where value(AFE_GAIN_RNG) is the corresponding value in dB for bits set for AFE_GAIN_RNG in DECPL_TEMP register |
FREQUENCY is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FREQUENCY_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FREQUENCY_TABLE.
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Burst frequency configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FREQ | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | FREQ | R/W | 0h | Burst frequency equation parameter: Frequency = 0.2 × FREQ + 30 [kHz] The valid FREQ parameter value range is from 0 to 250 (00h to FAh) |
DEADTIME is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DEADTIME_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DEADTIME_TABLE.
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Pulse deadtime and threshold deglitch configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR_CMP_DEGLTCH | PULSE_DT | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | THR_CMP_DEGLTCH | R/W | 0h | Threshold level comparator deglitch period: deglitch period = (THR_CMP_DEGLITCH × 8) [µs] |
3:0 | PULSE_DT | R/W | 0h | Burst Pulse Dead-Time: DeadTime = 0.0625 × PULSE_DT[µs] |
PULSE_P1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_PULSE_P1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_PULSE_P1_TABLE.
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Preset1 pulse burst number, IO pin control, and UART diagnostic configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IO_IF_SEL | UART_DIAG | IO_DIS | P1_PULSE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IO_IF_SEL | R/W | 0h | Interface Selection on IO pin: 0b = Time-Based Interface 1b = One-Wire UART Interface |
6 | UART_DIAG | R/W | 0h | UART Diagnostic Page Selection: 0b = Diagnostic bits related to UART interface 1b = Diagnostic bits related to System Diagnostics |
5 | IO_DIS | R/W | 0h | Disable IO pin transceiver: 0b = IO transceiver enabled 1b = IO transceiver disabled Note: Available only if IO_IF_SEL = 0 |
4:0 | P1_PULSE | R/W | 0h | Number of burst pulses for Preset1 Note: 0h means one pulse is generated on OUTA only |
PULSE_P2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_PULSE_P2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_PULSE_P2_TABLE.
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Preset2 pulse burst number and UART address configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
UART_ADDR | P2_PULSE | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | UART_ADDR | R/W | 0h | UART interface address |
4:0 | P2_PULSE | R/W | 0h | Number of burst pulses for Preset2 Note: 0h means one pulse is generated on OUTA only |
CURR_LIM_P1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_CURR_LIM_P1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_CURR_LIM_P1_TABLE.
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Preset1 driver current limit configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_CL | CURR_LIM1 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_CL | R/W | 0h | Disable Current Limit for Preset1 and Preset2 0b = current limit enabled 1b = current limit disabled |
5:0 | CURR_LIM1 | R/W | 0h | Driver Current Limit for Preset1 Current_Limit = 7 × CURR_LIM1 + 50 [mA] |
CURR_LIM_P2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_CURR_LIM_P2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_CURR_LIM_P2_TABLE.
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Preset2 current limit and low pass filter configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPF_CO | CURR_LIM2 | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | LPF_CO | R/W | 0h | Lowpass filter cutoff frequency: Cut off frequency = LPF_CO + 1 [kHz] |
5:0 | CURR_LIM2 | R/W | 0h | Driver current limit for Preset2 Current limit = 7 × CURR_LIM2 + 50 [mA] |
REC_LENGTH is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_REC_LENGTH_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_REC_LENGTH_TABLE.
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Echo data record period configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P1_REC | P2_REC | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | P1_REC | R/W | 0h | Preset1 record time length: Record time = 4.096 × (P1_REC + 1) [ms] |
3:0 | P2_REC | R/W | 0h | Preset2 record time length: Record time = 4.096 × (P2_REC + 1) [ms] |
FREQ_DIAG is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FREQ_DIAG_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FREQ_DIAG_TABLE.
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Frequency diagnostic configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDIAG_LEN | FDIAG_START | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | FDIAG_LEN | R/W | 0h | Frequency diagnostic window length: For value 0h, the diagnostic is disabled. For values 0 to Fh, the window length is given by 3 × FDIAG_LEN [Signal Periods] |
3:0 | FDIAG_START | R/W | 0h | Frequency diagnostic start time: Start time = 100 × FDIAG_START [µs] Note: this time is relative to the end-of-burst time |
SAT_FDIAG_TH is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_SAT_FDIAG_TH_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_SAT_FDIAG_TH_TABLE.
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Decay saturation threshold, frequency diagnostic error threshold, and Preset1 non-linear enable control configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FDIAG_ERR_TH | SAT_TH | P1_NLS_EN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | FDIAG_ERR_TH | R/W | 0h | Frequency diagnostic absolute error time threshold: threshold = (FDIAG_ERR_TH + 1) [µs] |
4:1 | SAT_TH | R/W | 0h | Saturation diagnostic threshold level. |
0 | P1_NLS_EN | R/W | 0h | Set high to enable Preset1 non-linear scaling |
FVOLT_DEC is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FVOLT_DEC_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_FVOLT_DEC_TABLE.
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Voltage thresholds and Preset2 non-linear scaling enable configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P2_NLS_EN | VPWR_OV_TH | LPM_TMR | FVOLT_ERR_TH | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | P2_NLS_EN | R/W | 0h | Set high to enable Preset2 non-linear scaling |
6:5 | VPWR_OV_TH | R/W | 0h | VPWR over voltage threshold select: 00b = 12.3 V 01b = 17.7 V 10b = 22.8 V 11b = 28.3 V |
4:3 | LPM_TMR | R/W | 0h | Low power mode enter time: 00b = 250 ms 01b = 500 ms 10b = 1 s 11b = 4s |
2:0 | FVOLT_ERR_TH | R/W | 0h | See section on System Diagnostics for Voltage diagnostic measurement: 000b = 1 001b = 2 010b = 3 011b = 4 100b = 5 101b = 6 110b = 7 111b = 8 |
DECPL_TEMP is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DECPL_TEMP_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DECPL_TEMP_TABLE.
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De-couple temperature and AFE gain range configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AFE_GAIN_RNG | LPM_EN | DECPL_TEMP_SEL | DECPL_T | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | AFE_GAIN_RNG | R/W | 0h | AFE gain range selection codes: 00b = 58 to 90 dB 01b = 52 to 84 dB 10b = 46 to 78 dB 11b = 32 to 64 dB |
5 | LPM_EN | R/W | 0h | PGA460 Low Power Mode Enable: 0b = Low power mode is disabled 1b = Low power mode is enabled |
4 | DECPL_TEMP_SEL | R/W | 0h | Decouple Time / Temperature Select: 0b = Time Decouple 1b = Temperature Decouple |
3:0 | DECPL_T | R/W | 0h | Secondary decouple time / temperature decouple If DECPL_TEMP_SEL = 0 (Time Decouple) Time = 4096 × (DECPL_T + 1) [µs] If DECPL_TEMP_SEL = 1 (Temperature Decouple) Temperature = 10 × DECPL_T - 40 [degC] |
DSP_SCALE is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DSP_SCALE_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_DSP_SCALE_TABLE.
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DSP non-linear scaling and noise level configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NOISE_LVL | SCALE_K | SCALE_N | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | NOISE_LVL | R/W | 0h | Value ranges from 0 to 31 with 1 LSB steps for digital gain values (Px_DIG_GAIN_LR) less than 8 If digital gain (Px_DIG_GAIN_LR) is larger than 8, then multiply the NOISE_LVL by Px_DIG_GAIN_LR/8 |
2 | SCALE_K | R/W | 0h | Non-Linear scaling exponent selection: 0b = 1.50 1b = 2.00 |
1:0 | SCALE_N | R/W | 0h | Selects the starting threshold level point from which the non-linear gain (if enabled) is applied: 00b = TH9 01b = TH10 10b = TH11 11b = TH12 |
TEMP_TRIM is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TEMP_TRIM_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_TEMP_TRIM_TABLE.
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Temperature sensor compensation values register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEMP_GAIN | TEMP_OFF | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TEMP_GAIN | R/W | 0h | Temperature scaling gain: signed value can range from -8 (1000b) to 7 (0111b) used for measured temperature value compensation |
3:0 | TEMP_OFF | R/W | 0h | Temperature Scaling Offset: signed value can range from -8 (1000b) to 7 (0111b) used for measured temperature value compensation |
P1_GAIN_CTRL is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_P1_GAIN_CTRL_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_P1_GAIN_CTRL_TABLE.
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Preset1 digital gain configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P1_DIG_GAIN_LR_ST | P1_DIG_GAIN_LR | P1_DIG_GAIN_SR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | P1_DIG_GAIN_LR_ST | R/W | 0h | Selects the starting Preset1 threshold level point from which the long range (LR) digital gain, P1_DIG_GAIN_LR, is applied 00b = TH9 01b = TH10 10b = TH11 11b = TH12 |
5:3 | P1_DIG_GAIN_LR | R/W | 0h | Preset1 Digital long range (LR) gain applied from the selected long range threshold level point to the end of the record period Applied to the thresholds set by P1_DIG_GAIN_LR_ST: 000b = multiplied by 1 001b = multiplied by 2 010b = multiplied by 4 011b = multiplied by 8 100b = multiplied by 16 101b = multiplied by 32 110b = invalid 111b = invalid |
2:0 | P1_DIG_GAIN_SR | R/W | 0h | Preset1 Digital short range (SR) gain applied from time zero to the start of the selected long range (LR) threshold level point: 000b = multiplied by 1 001b = multiplied by 2 010b = multiplied by 4 011b = multiplied by 8 100b = multiplied by 16 101b = multiplied by 32 110b = invalid 111b = invalid |
P2_GAIN_CTRL is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_P2_GAIN_CTRL_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_P2_GAIN_CTRL_TABLE.
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Preset2 digital gain configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P2_DIG_GAIN_LR_ST | P2_DIG_GAIN_LR | P2_DIG_GAIN_SR | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | P2_DIG_GAIN_LR_ST | R/W | 0h | Selects the starting Preset2 threshold level point from which the long range (LR) digital gain, P2_DIG_GAIN_LR, is applied 00b = TH9 01b = TH10 10b = TH11 11b = TH12 |
5:3 | P2_DIG_GAIN_LR | R/W | 0h | Preset2 Digital long range (LR) gain applied from the selected long range threshold level point to the end of the record period Applied to the thresholds set by P2_DIG_GAIN_LR_ST: 000b = multiplied by 1 001b = multiplied by 2 010b = multiplied by 4 011b = multiplied by 8 100b = multiplied by 16 101b = multiplied by 32 110b = invalid 111b = invalid |
2:0 | P2_DIG_GAIN_SR | R/W | 0h | Preset2 Digital short range (SR) gain applied from time zero to the start of the selected long range (LR) threshold level point: 000b = multiplied by 1 001b = multiplied by 2 010b = multiplied by 4 011b = multiplied by 8 100b = multiplied by 16 101b = multiplied by 32 110b = invalid 111b = invalid |
EE_CRC is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_EE_CRC_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/USER_EEPROM_EE_CRC_TABLE.
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User EEPROM space data CRC register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EE_CRC | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | EE_CRC | R/W | 0h | User EEPROM space data CRC value |
EE_CNTRL is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_EE_CNTRL_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_EE_CNTRL_TABLE.
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User EEPROM control register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DATADUMP_EN | EE_UNLCK | EE_PRGM_OK | EE_RLOAD | EE_PRGM | |||
RH/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DATADUMP_EN | RH/W | 0h | Data Dump Enable bit: 0b = Disabled 1b = Enabled |
6:3 | EE_UNLCK | R/W | 0h | EEPROM program enable unlock passcode register: The valid passcode for enabling EEPROM programming is 0xD. |
2 | EE_PRGM_OK | R | 0h | EEPROM programming status: 0b = EEPROM was not programmed successfully 1b = EEPROM was programmed successfully |
1 | EE_RLOAD | R/W | 0h | EEPROM Reload Trigger: 0b = Disabled 1b = Reload Data from EEPROM |
0 | EE_PRGM | R/W | 0h | EEPROM Program Trigger: 0b = Disabled 1b = Program Data to EEPROM |
BPF_A2_MSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A2_MSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A2_MSB_TABLE.
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BPF A2 coefficient most-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_A2_MSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_A2_MSB | R/W | 0h | Bandpass filter A2 coefficient most-significant byte value |
BPF_A2_LSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A2_LSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A2_LSB_TABLE.
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BPF A2 coefficient least-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_A2_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_A2_LSB | R/W | 0h | Bandpass filter A2 coefficient least-significant byte value |
BPF_A3_MSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A3_MSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A3_MSB_TABLE.
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BPF A3 coefficient most-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_A3_MSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_A3_MSB | R/W | 0h | Bandpass filter A3 coefficient most-significant byte value |
BPF_A3_LSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A3_LSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_A3_LSB_TABLE.
Return to Summary Table.
BPF A3 coefficient least-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_A3_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_A3_LSB | R/W | 0h | Bandpass filter A3 coefficient least-significant byte value |
BPF_B1_MSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_B1_MSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_B1_MSB_TABLE.
Return to Summary Table.
BPF B1 coefficient most-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_B1_MSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_B1_MSB | R/W | 0h | Bandpass filter B1 coefficient most-significant byte value |
BPF_B1_LSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_B1_LSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_BPF_B1_LSB_TABLE.
Return to Summary Table.
BPF B1 coefficient least-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BPF_B1_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | BPF_B1_LSB | R/W | 0h | Bandpass filter B1 coefficient least-significant byte value |
LPF_A2_MSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_A2_MSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_A2_MSB_TABLE.
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LPF A2 coefficient most-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LPF_A2_MSB | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6:0 | LPF_A2_MSB | R/W | 0h | Lowpass filter A2 coefficient most-significant byte value |
LPF_A2_LSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_A2_LSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_A2_LSB_TABLE.
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LPF A2 coefficient least-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPF_A2_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | LPF_A2_LSB | R/W | 0h | Lowpass filter A2 coefficient least-significant byte value |
LPF_B1_MSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_B1_MSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_B1_MSB_TABLE.
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LPF B1 coefficient most-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LPF_B1_MSB | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6:0 | LPF_B1_MSB | R/W | 0h | Lowpass filter B1 coefficient most-significant byte value |
LPF_B1_LSB is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_B1_LSB_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_LPF_B1_LSB_TABLE.
Return to Summary Table.
LPF B1 coefficient least-significant byte configuration
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LPF_B1_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | LPF_B1_LSB | R/W | 0h | Lowpass filter B1 coefficient least-significant byte value |
TEST_MUX is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_TEST_MUX_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_TEST_MUX_TABLE.
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Test multiplexers configuration register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST_MUX | RESERVED | SAMPLE_SEL | DP_MUX | ||||
R/W-0h | R-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | TEST_MUX | R/W | 0h | Multiplexer output on the TEST Pin: 000b = GND ("Mux Off") 001b = Analog Front End output 010b = Reserved 011b = Reserved 100b = 8MHz clock 101b = ADC sample output clock 110b = Reserved 111b = Reserved Note 1 000b through 011b are analog output signals Note 2 100b through 111b are digital output signals |
4 | RESERVED | R | 0h | Reserved |
3 | SAMPLE_SEL | R/W | 0h | Data path sample select: 0b = 8 bit sample output at 1 µs per sample 1b = 12 bit sample output at 2 µs per sample Note: For use with DP_MUX parameter values 001b to 100b |
2:0 | DP_MUX | R/W | 0h | Data path multiplexer source select codes: 000b = Disabled 001b = LPF output 010b = Rectifier output 011b = BPF output 100b = ADC output 101b = Not used 110b = Not used 111b = Not used |
DEV_STAT0 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_DEV_STAT0_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_DEV_STAT0_TABLE.
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Device Status register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV_ID | OPT_ID | CMW_WU_ERR | THR_CRC_ERR | EE_CRC_ERR | TRIM_CRC_ERR | ||
R-2h | R-0h | R-0h | R-1h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | REV_ID | R | 2h | Device Revision Identification |
5:4 | OPT_ID | R | 0h | Device Option Identification |
3 | CMW_WU_ERR | R | 0h | Wakeup Error indicator: 0 = no error 1 = user tried to send a command before the wake up sequence is done |
2 | THR_CRC_ERR | R | 1h | Threshold map configuration register data CRC error status: 0 = No error 1 = CRC error detected This flag is asserted upon device power-up to indicate the un-initialized state of the threshold map configuration registers. |
1 | EE_CRC_ERR | R | 0h | User EEPROM space data CRC error status: 0 = No error 1 = CRC error detected |
0 | TRIM_CRC_ERR | R | 0h | Trim EEPROM space data CRC error status: 0 = No error 1 = CRC error detected |
DEV_STAT1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_DEV_STAT1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/DEV_STAT_CFG_DEV_STAT1_TABLE.
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Device status register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TSD_PROT | IOREG_OV | IOREG_UV | AVDD_OV | AVDD_UV | VPWR_OV | VPWR_UV |
R-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h | RC-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | Reserved |
6 | TSD_PROT | RC | 0h | Thermal shut-down protection status: 0 = No thermal shutdown has occurred 1 = Thermal shutdown has occurred |
5 | IOREG_OV | RC | 0h | IOREG pin over voltage status: 0 = No error 1 = IOREG over voltage error |
4 | IOREG_UV | RC | 0h | IOREG pin under voltage status: 0 = No error 1 = IOREG under voltage error |
3 | AVDD_OV | RC | 0h | AVDD pin over voltage status: 0 = No error 1 = AVDD over voltage error |
2 | AVDD_UV | RC | 0h | AVDD pin under voltage status: 0 = No Error 1 = AVDD Under voltage error |
1 | VPWR_OV | RC | 0h | VPWR pin over voltage status: 0 = No error 1 = VPWR over voltage error |
0 | VPWR_UV | RC | 0h | VPWR pin under voltage status: 0 = No error 1 = VPWR under voltage Error |
P1_THR_0 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_0_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_0_TABLE.
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Preset1 threshold map segment configuration register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T1 | TH_P1_T2 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T1 | R/W | X | Preset1 Threshold T1 absolute time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T2 | R/W | X | Preset1 Threshold T2 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_1_TABLE.
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Preset1 threshold map segment configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T3 | TH_P1_T4 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T3 | R/W | X | Preset1 Threshold T3 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T4 | R/W | X | Preset1 Threshold T4 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_2_TABLE.
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Preset1 threshold map segment configuration register 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T5 | TH_P1_T6 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T5 | R/W | X | Preset1 Threshold T5 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T6 | R/W | X | Preset1 Threshold T6 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_3 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_3_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_3_TABLE.
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Preset1 threshold map segment configuration register 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T7 | TH_P1_T8 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T7 | R/W | X | Preset1 Threshold T7 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T8 | R/W | X | Preset1 Threshold T8 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_4 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_4_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_4_TABLE.
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Preset1 threshold map segment configuration register 4
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T9 | TH_P1_T10 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T9 | R/W | X | Preset1 Threshold T9 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T10 | R/W | X | Preset1 Threshold T10 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_5 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_5_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_5_TABLE.
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Preset1 threshold map segment configuration register 5
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_T11 | TH_P1_T12 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_T11 | R/W | X | Preset1 Threshold T11 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P1_T12 | R/W | X | Preset1 Threshold T12 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P1_THR_6 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_6_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_6_TABLE.
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Preset1 threshold map segment configuration register 6
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L1 | TH_P1_L2 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | TH_P1_L1 | R/W | X | Preset1 Threshold L1 level This bit-field powers-up un-initialized. |
2:0 | TH_P1_L2 | R/W | X | Preset1 Threshold L2 level bits (Bit4 to Bit2) This bit-field powers-up un-initialized. |
P1_THR_7 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_7_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_7_TABLE.
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Preset1 threshold map segment configuration register 7
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L2 | TH_P1_L3 | TH_P1_L4 | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | TH_P1_L2 | R/W | X | Preset1 Threshold L2 level (Bit1 to Bit0) This bit-field powers-up un-initialized. |
5:1 | TH_P1_L3 | R/W | X | Preset1 Threshold L3 level This bit-field powers-up un-initialized. |
0 | TH_P1_L4 | R/W | X | Preset1 Threshold L4 level (Bit4) This bit-field powers-up un-initialized. |
P1_THR_8 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_8_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_8_TABLE.
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Preset1 threshold map segment configuration register 8
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L4 | TH_P1_L5 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P1_L4 | R/W | X | Preset1 Threshold L4 level (Bits3 to Bit0) This bit-field powers-up un-initialized. |
3:0 | TH_P1_L5 | R/W | X | Preset1 Threshold L5 level (Bit4 to Bit1) This bit-field powers-up un-initialized. |
P1_THR_9 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_9_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_9_TABLE.
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Preset1 threshold map segment configuration register 9
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L5 | TH_P1_L6 | TH_P1_L7 | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TH_P1_L5 | R/W | X | Preset1 Threshold L5 level (Bit0) This bit-field powers-up un-initialized. |
6:2 | TH_P1_L6 | R/W | X | Preset1 Threshold L6 level This bit-field powers-up un-initialized. |
1:0 | TH_P1_L7 | R/W | X | Preset1 Threshold L7 level (Bits4 to Bit3) This bit-field powers-up un-initialized. |
P1_THR_10 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_10_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_10_TABLE.
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Preset1 threshold map segment configuration register 10
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L7 | TH_P1_L8 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | TH_P1_L7 | R/W | X | Preset1 Threshold L7 Level (Bit2 to Bit0) This bit-field powers-up un-initialized. |
4:0 | TH_P1_L8 | R/W | X | Preset1 Threshold L8 level This bit-field powers-up un-initialized. |
P1_THR_11 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_11_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_11_TABLE.
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Preset1 threshold map segment configuration register 11
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L9 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P1_L9 | R/W | X | Threshold L9 level This bit-field powers-up un-initialized. |
P1_THR_12 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_12_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_12_TABLE.
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Preset1 threshold map segment configuration register 12
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L10 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P1_L10 | R/W | X | Preset1 Threshold L10 Level This bit-field powers-up un-initialized. |
P1_THR_13 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_13_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_13_TABLE.
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Preset1 threshold map segment configuration register 13
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L11 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P1_L11 | R/W | X | Preset1 Threshold L11 Level This bit-field powers-up un-initialized. |
P1_THR_14 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_14_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_14_TABLE.
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Preset1 threshold map segment configuration register 14
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P1_L12 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P1_L12 | R/W | X | Preset1 Threshold L12 Level. This bit-field powers-up un-initialized. |
P1_THR_15 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_15_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P1_THR_15_TABLE.
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Preset1 threshold map segment configuration register 15
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH_P1_OFF | ||||||
R-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R | X | Reserved |
3:0 | TH_P1_OFF | R/W | X | Preset1 Threshold level Offset with values from 7 to -8 using signed magnitude representation with MSB as the sign bit This bit-field powers-up un-initialized. |
P2_THR_0 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_0_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_0_TABLE.
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Preset2 threshold map segment configuration register 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T1 | TH_P2_T2 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T1 | R/W | X | Preset2 Threshold T1 absolute time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T2 | R/W | X | Preset2 Threshold T2 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_1 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_1_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_1_TABLE.
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Preset2 threshold map segment configuration register 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T3 | TH_P2_T4 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T3 | R/W | X | Preset2 Threshold T3 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T4 | R/W | X | Preset2 Threshold T4 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_2 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_2_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_2_TABLE.
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Preset2 threshold map segment configuration register 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T5 | TH_P2_T6 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T5 | R/W | X | Preset2 Threshold T5 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T6 | R/W | X | Preset2 Threshold T6 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_3 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_3_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_3_TABLE.
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Preset2 threshold map segment configuration register 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T7 | TH_P2_T8 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T7 | R/W | X | Preset2 Threshold T7 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T8 | R/W | X | Preset2 Threshold T8 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_4 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_4_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_4_TABLE.
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Preset2 threshold map segment configuration register 4
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T9 | TH_P2_T10 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T9 | R/W | X | Preset2 Threshold T9 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T10 | R/W | X | Preset2 Threshold T10 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_5 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_5_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_5_TABLE.
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Preset2 threshold map segment configuration register 5
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_T11 | TH_P2_T12 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_T11 | R/W | X | Preset2 Threshold T11 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
3:0 | TH_P2_T12 | R/W | X | Preset2 Threshold T12 delta time: 0000b = 100 µs 0001b = 200 µs 0010b = 300 µs 0011b = 400 µs 0100b = 600 µs 0101b = 800 µs 0110b = 1000 µs 0111b = 1200 µs 1000b = 1400 µs 1001b = 2000 µs 1010b = 2400 µs 1011b = 3200 µs 1100b = 4000 µs 1101b = 5200 µs 1110b = 6400 µs 1111b = 8000 µs This bit-field powers-up un-initialized. |
P2_THR_6 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_6_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_6_TABLE.
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Preset2 threshold map segment configuration register 6
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L1 | TH_P2_L2 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:3 | TH_P2_L1 | R/W | X | Preset2 Threshold L1 level This bit-field powers-up un-initialized. |
2:0 | TH_P2_L2 | R/W | X | Preset2 Threshold L2 level (Bit4 to Bit2) This bit-field powers-up un-initialized. |
P2_THR_7 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_7_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_7_TABLE.
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Preset2 threshold map segment configuration register 7
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L2 | TH_P2_L3 | TH_P2_L4 | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | TH_P2_L2 | R/W | X | Preset2 Threshold L2 level (Bit1 to Bit0) This bit-field powers-up un-initialized. |
5:1 | TH_P2_L3 | R/W | X | Preset2 Threshold L3 level This bit-field powers-up un-initialized. |
0 | TH_P2_L4 | R/W | X | Preset2 Threshold L4 level (Bit4) This bit-field powers-up un-initialized. |
P2_THR_8 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_8_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_8_TABLE.
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Preset2 threshold map segment configuration register 8
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L4 | TH_P2_L5 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | TH_P2_L4 | R/W | X | Preset2 Threshold L4 level (Bit3 to Bit0) This bit-field powers-up un-initialized. |
3:0 | TH_P2_L5 | R/W | X | Preset2 Threshold L5 level (Bit4 to Bit1) This bit-field powers-up un-initialized. |
P2_THR_9 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_9_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_9_TABLE.
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Preset2 threshold map segment configuration register 9
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L5 | TH_P2_L6 | TH_P2_L7 | |||||
R/W-X | R/W-X | R/W-X | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TH_P2_L5 | R/W | X | Preset2 Threshold L5 level (Bit0) This bit-field powers-up un-initialized. |
6:2 | TH_P2_L6 | R/W | X | Preset2 Threshold L6 level This bit-field powers-up un-initialized. |
1:0 | TH_P2_L7 | R/W | X | Preset2 Threshold L7 level (Bit4 to Bit3) This bit-field powers-up un-initialized. |
P2_THR_10 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_10_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_10_TABLE.
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Preset2 threshold map segment configuration register 10
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L7 | TH_P2_L8 | ||||||
R/W-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:5 | TH_P2_L7 | R/W | X | Preset2 Threshold L7 level (Bit2 to Bit0) This bit-field powers-up un-initialized. |
4:0 | TH_P2_L8 | R/W | X | Preset2 Threshold L8 level This bit-field powers-up un-initialized. |
P2_THR_11 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_11_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_11_TABLE.
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Preset2 threshold map segment configuration register 11
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L9 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P2_L9 | R/W | X | Preset2 Threshold L9 level This bit-field powers-up un-initialized. |
P2_THR_12 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_12_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_12_TABLE.
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Preset2 threshold map segment configuration register 12
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L10 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P2_L10 | R/W | X | Preset2 Threshold L10 Level This bit-field powers-up un-initialized. |
P2_THR_13 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_13_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_13_TABLE.
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Preset2 threshold map segment configuration register 13
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L11 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P2_L11 | R/W | X | Preset2 Threshold L11 Level This bit-field powers-up un-initialized. |
P2_THR_14 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_14_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_14_TABLE.
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Preset2 threshold map segment configuration register 14
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH_P2_L12 | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | TH_P2_L12 | R/W | X | Preset2 Threshold L12 Level This bit-field powers-up un-initialized. |
P2_THR_15 is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_15_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_P2_THR_15_TABLE.
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Preset2 threshold map segment configuration register 15
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TH_P2_OFF | ||||||
R-X | R/W-X | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | RESERVED | R | X | Reserved |
3:0 | TH_P2_OFF | R/W | X | Preset2 Threshold level Offset with values from 7 to -8 using signed magnitude representation with MSB as the sign bit This bit-field powers-up un-initialized. |
THR_CRC is shown in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_THR_CRC_FIGURE and described in #GUID-A4B7F9B0-DD4E-4482-8760-09D6CBA740CC/THRESHOLD_THR_CRC_TABLE.
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Threshold map configuration registers data CRC register
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
THR_CRC | |||||||
R/W-X | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | THR_CRC | R/W | X | Threshold map configuration registers data CRC value: This read-only register is updated whenever a threshold map configuration register gets updated This bit-field powers-up un-initialized. |