SLLSEF3C June   2013  – March 2021 SN6501-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 15
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Push-Pull Converter
      2. 8.3.2 Core Magnetization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Start-Up Mode
      2. 8.4.2 Operating Mode
      3. 8.4.3 Off-Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 SN6501 Drive Capability
        2. 9.2.2.2 LDO Selection
        3. 9.2.2.3 Diode Selection
        4. 9.2.2.4 Capacitor Selection
        5. 9.2.2.5 Transformer Selection
          1. 9.2.2.5.1 V-t Product Calculation
          2. 9.2.2.5.2 Turns Ratio Estimate
          3. 9.2.2.5.3 Recommended Transformers
      3. 9.2.3 Application Curve
      4. 9.2.4 Higher Output Voltage Designs
      5. 9.2.5 Application Circuits
  10. 10Power Supply Recommendations
    1. 10.1 43
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.4 Capacitor Selection

The capacitors in the converter circuit in Figure 9-7 are multi-layer ceramic chip (MLCC) capacitors.

As with all high speed CMOS ICs, the SN6501 requires a bypass capacitor in the range of 10 nF to 100 nF.

The input bulk capacitor at the center-tap of the primary supports large currents into the primary during the fast switching transients. For minimum ripple make this capacitor 1 μF to 10 μF. In a 2-layer PCB design with a dedicated ground plane, place this capacitor close to the primary center-tap to minimize trace inductance. In a 4-layer board design with low-inductance reference planes for ground and VIN, the capacitor can be placed at the supply entrance of the board. To ensure low-inductance paths use two vias in parallel for each connection to a reference plane or to the primary center-tap.

The bulk capacitor at the rectifier output smoothes the output voltage. Make this capacitor 1 μF to 10 μF.

The small capacitor at the regulator input is not necessarily required. However, good analog design practice suggests, using a small value of 47 nF to 100 nF improves the regulator’s transient response and noise rejection.

The LDO output capacitor buffers the regulated output for the subsequent isolator and transceiver circuitry. The choice of output capacitor depends on the LDO stability requirements specified in the data sheet. However, in most cases, a low-ESR ceramic capacitor in the range of 4.7 μF to 10 μF will satisfy these requirements.