SLLS740C March   2007  – February 2024 SN65C1167E , SN65C1168E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Driver Output and Receiver Input ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Driver Section Electrical Characteristics
    6. 5.6 Receiver Section Electrical Characteristics
    7. 5.7 Driver Section Switching Characteristics
    8. 5.8 Receiver Section Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active High Driver Output Enables
      2. 7.3.2 Active Low Receiver Enables
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Driver Section Switching Characteristics

over recommended supply voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPHLPropagation delay time, high- to low-level outputR1 = R2 = 50Ω,
C1 = C2 = C3 = 40pF,
See Figure 6-2		R3 = 500Ω,
S1 is open,
816ns
tPLHPropagation delay time, low- to high-level output816ns
tsk(p)Pulse skew1.54ns
trRise timeR1 = R2 = 50Ω,
C1 = C2 = C3 = 40pF,
See Figure 6-3		R3 = 500Ω,
S1 is open,		58ns
tfFall time58ns
tPZHOutput-enable time to high levelR1 = R2 = 50Ω,
C1 = C2 = C3 = 40pF,
See Figure 6-4		R3 = 500Ω,
S1 is closed,		1019ns
tPZLOutput-enable time to low level1019ns
tPHZOutput-disable time from high levelR1 = R2 = 50Ω,
C1 = C2 = C3 = 40pF,
See Figure 6-4		R3 = 500Ω,
S1 is closed,		716ns
tPLZOutput-disable time from low level716ns
fSWMaximum switching frequencyR1 = R2 = 50Ω,
C1 = C2 = C3 = 40pF,
See Figure 6-3		R3 = 500Ω,
S1 is open,		20MHz
(1) All typical values are at VCC = 5V and TA = 25°C.