SLLSEO9C March   2016  – August 2019 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, Power Supply
    6. 6.6 Electrical Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 HS Receive Equalization
      2. 7.3.2 HS TX Edge Rate Control
      3. 7.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 7.3.4 Dynamic De-skew
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 LP Mode
      3. 7.4.3 ULPS Mode
      4. 7.4.4 HS Mode
    5. 7.5 Register Maps
      1. 7.5.1  BIT Access Tag Conventions
      2. 7.5.2  Standard CSR Registers (address = 0x000 - 0x07)
        1. Table 6. Standard CSR Registers (0x000 - 0x07)
      3. 7.5.3  Standard CSR Register (address = 0x08)
        1. Table 7. Standard CSR Register (0x08)
      4. 7.5.4  Standard CSR Register (address = 0x09)
        1. Table 8. Standard CSR Register (0x09)
      5. 7.5.5  Standard CSR Register (address = 0x0A)
        1. Table 9. Standard CSR Register (0x0A)
      6. 7.5.6  Standard CSR Register (address = 0x0B)
        1. Table 10. Standard CSR Register (0x0B)
      7. 7.5.7  Standard CSR Register (address = 0x0D)
        1. Table 11. Standard CSR Register (0x0D)
      8. 7.5.8  Standard CSR Register (address = 0x0E)
        1. Table 12. Standard CSR Register (0x0E)
      9. 7.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
        1. Table 13. Standard CSR Register (0x10)
      10. 7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
        1. Table 14. Standard CSR Register (0x11)
  8. 8 Application and Implementation
    1. 8.1 Application Information,
    2. 8.2 Typical Application, CSI-2 Implementations
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Reset Implementation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RHR Package
28 Pin (WQFN)
Top View

Pin Functions

PIN I/O INTERNAL
PULLUP/PULLDOWN		 DESCRIPTION
NAME NO.
DA0P 1 100-Ω Differential Input CSI-2/DSI Lane 0 Differential positive Input. Supports DSI LP Backchannel. If unused, this pin should be tied to GND.
DA0N 2 CSI-2/DSI Lane 0 Differential negative Input. Supports DSI LP Backchannel. If unused, this pin should be tied to GND.
DA1P 3 100-Ω Differential Input (Failsafe) CSI-2/DSI Lane 1 Differential positive Input. If unused, this pin should be tied to GND.
DA1N 4 CSI-2/DSI Lane 1 Differential negative input. If unused, this pin should be tied to GND.
DACP 5 100-Ω Differential Input (Failsafe) CSI-2/DSI Differential Clock positive Input
DACN 6 CSI-2/DSI Differential Clock negative Input
DA2P 7 100-Ω Differential Input (Failsafe) CSI-2/DSI Lane 2 Differential positive Input. If unused, this pin should be tied to GND.
DA2N 8 CSI-2/DSI Lane 2 Differential negative Input. If unused, this pin should be tied to GND.
DA3P 9 100-Ω Differential Input (Failsafe) CSI-2/DSI Lane 3 Differential positive Input. If unused, this pin should be tied to GND.
DA3N 10 CSI-2/DSI Lane 3 Differential negative Input. If unused, this pin should be tied to GND.
VCC 11 Power 1.8V (±10%) Supply.
VREG_OUT 12 Power 1.2 V Regulator Output. Requires a 0.1 µF capacitor to GND.
EQ/SCL 13 I/O
(3-level)		 PU (100K)
PD (100K) 		RX Equalization Select. Pin state sampled on rising edge of RSTN. This pin also functions as I2C SCL pin.
VIL = 0 dB
VIM = 2.5 dB
VIH = 5 dB
ERC/SDA 14 I/O
(3-level)		 PU (100K)
PD (100K)		 Edge Rate Control for DB[4:0]P/N High speed transmitter rise and fall time. Pin state sampled on rising edge of RSTN. This pin also functions as I2C SDA pin.
VIL = 200 ps typical
VIM = 150 ps typical
VIH = 250 ps typical
DB3N 15 100-Ω Differential Output CSI-2/DSI Lane 3 Differential negative Output. If unused, this pin should be left unconnected.
DB3P 16 CSI-2/DSI Lane 3 Differential positive Output. If unused, this pin should be left unconnected.
DB2N 17 100-Ω Differential Output CSI-2/DSI Lane 2 Differential negative Output. If unused, this pin should be left unconnected.
DB2P 18 CSI-2/DSI Lane 2 Differential positive Output. If unused, this pin should be left unconnected.
DBCN 19 100-Ω Differential Output CSI-2/DSI Differential Clock negative Output
DBCP 20 CSI-2/DSI Differential Clock positive Output
DB1N 21 100-Ω Differential Output CSI-2/DSI Lane 1 Differential negative Output. If unused, this pin should be left unconnected.
DB1P 22 CSI-2/DSI Lane 1 Differential positive Output. If unused, this pin should be left unconnected.
DB0N 23 100-Ω Differential Output CSI-2/DSI Lane 0 Differential negative Output. Supports DSI LP Back channel. If unused, this pin should be left unconnected.
DB0P 24 CSI-2/DSI Lane 0 Differential positive Output. Supports DSI LP Back channel. If unused, this pin should be left unconnected.
VDD 25 Power This pin must be connected to the VREG_OUT pin through at least a 10-mil trace and a 0.1 µF capacitor to ground.
PRE_CFG1 26 I/O
(3-level)		 PU (100K)
PD (100K) 		Controls DPHY TX HS pre-emphasis level and the LP TX rise and fall times. Pin state is sampled on the rising edge of RSTN.
VIL = 0 dB
VIM = 0 dB
VIH = 2.5 dB
VSADJ_CFG0 27 I
(3-level)		 PU (100K)
PD (100K)		 Controls output voltage swing for DB HS transmitters and the LP TX rise and fall times. Pin state is sampled on the rising edge of RSTN. Refer to Table 3 for details on voltage swing settings based on this pin and PRE_CFG1 sampled state.
VIL = 200 mV or 220 mV based on PRE_CFG1 sampled state.
VIM = 200 mV typical
VIH = 220 mV typical
RSTN 28 I PU (300K) Reset, active low. When low, all internal CSR are reset to default and DPHY440 is placed in low power state.
GND Thermal pad GND Ground.