SLLS552G December   2002  – September 2022 SN65HVD20 , SN65HVD21 , SN65HVD22 , SN65HVD23 , SN65HVD24

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Driver Electrical Characteristics
    6. 8.6  Receiver Electrical Characteristics
    7. 8.7  Driver Switching Characteristics
    8. 8.8  Receiver Switching Characteristics
    9. 8.9  Receiver Equalization Characteristics
    10. 8.10 Power Dissipation
    11. 8.11 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Test Mode Driver Disable
      2. 10.4.2 Equivalent Input and Output Schematic Diagrams
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Noise Considerations for Equalized Receivers
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)(1)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VIT(+)Positive-going differential input voltage thresholdSee Figure 9-10VO = 2.4 V, IO = –8 mA60200mV
VIT(–)Negative-going differential input voltage thresholdVO = 0.4 V, IO = 8 mA–200–60
VHYSHysteresis voltage (VIT+ – VIT–)100130mV
VIT(F+)Positive-going differential input failsafe voltage thresholdSee Figure 9-15VCM = –7 V to 12 V40120200mV
VCM = –20 V to 25 V120250
VIT(F–)Negative-going differential input failsafe voltage thresholdSee Figure 9-15VCM = –7 V to 12 V–200–120–40mV
VCM = –20 V to 25 V–250–120
VIKInput clamp voltageII = –18 mA–1.5V
VOHHigh-level output voltageVID = 200 mV, IOH = –8 mA, See Figure 9-114V
VOLLow-level output voltageVID = –200 mV, IOL = 8 mA, See Figure 9-110.4V
II(BUS)Bus input current (power on or power off)VI = –7 to 12 V,
Other input = 0 V		SN65HVD2[0,3]–400500µA
SN65HVD2[1,2,4]–100125
VI = –20 to 25 V,
Other input = 0 V		SN65HVD2[0,3]–8001000
SN65HVD2[1,2,4]–200250
IIInput currentRE–100100µA
RIInput resistanceSN65HVD2[0,3]24kΩ
SN65HVD2[1,2,4]96
CIDDifferential input capacitanceVID = 0.5 + 0.4 sine (2π × 1.5 × 106t)20pF
(1) All typical values are at VCC = 5 V and 25°C.