SLLSEA2D December   2011  – May 2015 SN65HVD255 , SN65HVD256 , SN65HVD257

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Options
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Power Dissipation
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant Timeout (DTO)
      2. 9.3.2 RXD Dominant Timeout (SN65HVD257)
      3. 9.3.3 Thermal Shutdown
      4. 9.3.4 Undervoltage Lockout
      5. 9.3.5 FAULT Pin (SN65HVD257)
      6. 9.3.6 Unpowered Device
      7. 9.3.7 Floating Pins
      8. 9.3.8 CAN Bus Short-Circuit Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operating Modes
      2. 9.4.2 Can Bus States
      3. 9.4.3 Normal Mode
      4. 9.4.4 Silent Mode
      5. 9.4.5 Digital Inputs and Outputs
        1. 9.4.5.1 5-V VCC Only Devices (SN65HVD255 and SN65HVD257)
        2. 9.4.5.2 5-V VCC With VRXD RXD Output Supply Devices (SN65HVD256)
        3. 9.4.5.3 5-V VCC with FAULT Open-Drain Output Device (SN65HVD257)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bus Loading, Length, and Number of Nodes
    2. 10.2 Typical Applications
      1. 10.2.1 Typical 5-V Microcontroller Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 CAN Termination
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Example: Functional Safety Using the SN65HVD257 in a Redundant Physical Layer CAN Network Topology
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Typical 3.3-V Microcontroller Application
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

For the PCB design to be successful, start with the design of the protection and filtering circuitry because ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-GHz and high frequency layout techniques must be applied during PCB design. On chip IEC ESD protection is good for laboratory and portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices at the bus connectors. Placement at the connector also prevents these harsh transient events from propagating further into the PCB and system.

Use VCC and ground planes to provide low inductance.

NOTE

High frequency current follows the path of least inductance and not the path of least resistance.

Design the bus protection components in the direction of the signal path. Do not force the transient current to divert from the signal path to reach the protection device. Below is a list of layout recommendations when designing a CAN transceiver into an application.

  • Transient Protection on CANH and CANL: Transient Voltage Suppression (TVS) and capacitors (D1, C5 and C7 shown in Figure 23) can be used to protect the system level transients like EFT, IEC ESD, and Surge. These devices must be placed as close to the connector as possible. This prevents the transient energy and noise from penetrating into other nets on the board.
  • Bus Termination on CANH and CANL:Figure 23 shows split termination where the termination is split into two resistors, R5 and R6, with the center or split tap of the termination connected to ground through capacitor C6. Split termination provides common mode filtering for the bus. When termination is placed on the board instead of directly on the bus, care must be taken to ensure the terminating node is not removed from the bus, as this causes signal integrity issues if the bus is not properly terminated on both ends.
  • Decoupling Capacitors on VCC and VRXD: Bypass and bulk capacitors must be placed as close as possible to the supply pins of transceiver (examples are C2, C3, C5, and C6).
  • Ground and power connections: Use at least two vias for VCC, VIO, and ground connections of bypass capacitors and protection devices to minimize trace and via inductance.
  • Digital inputs and outputs: To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3, R4, and R5.
  • Filtering noise on digital inputs and outputs: To filter noise on the digital I/O lines, a capacitor may be used close to the input side of the I/O as shown by C1 and C4.
  • External pull-up resistors on input and output pins: Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10-kΩ pullup or pulldown resistor must be used to bias the state of the pins during transient events.
  • Fault Output Pin (SN65HVD257 only): Because the FAULT output pin is an open drain output, an external pullup resistor is required to pull the pin voltage high for normal operation (R5).
  • VRXD Supply (SN65HVD256 only): The SN65HVD256 device will need additional bypass capacitors for the VRXD supply shown with C5 and C6.
  • TXD input pin: If an open-drain host processor is used to drive the TXD pin of the device, an external pullup resistor between 1 kΩ and 10 kΩ must be used to help drive the recessive input state of the device (weak internal pullup resistor).

12.2 Layout Example

SN65HVD255 SN65HVD256 SN65HVD257 layout_SLLSEA2.gifFigure 23. Layout Example