SLLSEU5 Data sheet

SLLSEU5 December 2016 SN65LBC175A-EP

PRODUCTION DATA.

Package Options

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_CC⁽²⁾	–0.3	6	V
Voltage at any bus input (steady state), A and B	–10	15	V
Voltage at any bus (transient pulse through 100 Ω, see Figure 10)	–30	30	V
Input voltage at 1,2EN and 3,4EN, V_I	–0.5	V_CC + 0.5	V
Receiver output current, I_O	–10	10	mA
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to GND and are steady-state (unless otherwise specified).

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	A and B to GND	±6000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±5000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	All pins	±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage		4.75	5	5.25	V
	Voltage at any bus terminal	A, B	–7		12	V
V_IH	High-level input voltage	EN	2		V_CC	V
V_IL	Low-level input voltage	EN	0		0.8	V
	Output current	Y	–8		8	mA
T_J	Junction temperature		–55		125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN65LBC175A-EP	UNITS
		D (SOIC)
		16 PINS
θ_JA	Junction-to-ambient thermal resistance	78	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance	39.5	°C/W
θ_JB	Junction-to-board thermal resistance	35.4	°C/W
ψ_JT	Junction-to-top characterization parameter	8.5	°C/W
ψ_JB	Junction-to-board characterization parameter	35.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating conditions

PARAMETER			TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
V_IT+	Positive-going differential input voltage threshold		–7 V ≤ V_CM ≤ 12 V (V_CM = (V_A + V_B) / 2)			–80	–10	mV
V_IT-	Negative-going differential input voltage threshold		–7 V ≤ V_CM ≤ 12 V (V_CM = (V_A + V_B) / 2)		–200	–120		mV
V_HYS	Hysteresis voltage (V_IT+ – V_IT–)					–40		mV
V_IK	Input clamp voltage		I_I = –18 mA		–1.5	–0.8		V
V_OH	High-level output voltage		V_ID = 200 mV, I_OH = –8 mA	See Figure 6	2.7	4.8		V
V_OL	Low-level output voltage		V_ID = –200 mV, I_OL = 8 mA	See Figure 6		0.2	0.4	V
I_OZ	High-impedance-state output current		V_O = 0 V to V_CC		–1		1	µA
I_I	Line input current		Other input at 0 V, V_CC = 0 V or 5 V	V_I = 12 V			0.9	mA
I_I	Line input current		Other input at 0 V, V_CC = 0 V or 5 V	V_I = –7 V	–0.7			mA
I_IH	High-level input current	Enable inputs					110	µA
I_IL	Low-level input current	Enable inputs			–100			µA
R_I	Input resistance	A, B inputs			12			kΩ
I_CC	Supply current		V_ID = 5 V	1,2EN, 3,4EN at 0 V			32	µA
I_CC	Supply current		No load	1,2EN, 3,4EN at V_CC		11	16	mA

(1) All typical values are at V_CC = 5 V and 25°C.

6.6 Switching Characteristics

Over recommended operating conditions

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	Output rise time	V_ID = –3 V to 3 V, See Figure 7		2	7	ns
t_f	Output fall time			2	7	ns
t_PLH	Propagation delay time, low-to-high level output		8	12	18	ns
t_PHL	Propagation delay time, high-to-low level output		8	12	18	ns
t_PZH	Propagation delay time, high-impedance to high-level output	See Figure 8		27	39	ns
t_PHZ	Propagation delay time, high-level-output to high-impedance	See Figure 8		7	24	ns
t_PZL	Propagation delay time, high-impedance to low-level output	See Figure 9		29	39	ns
t_PLZ	Propagation delay time, low-level-output to high-impedance	See Figure 9		12	18	ns
t_sk(p)	Pulse skew (\|t_PLH – t_PHL\|)			0.2	2	ns
t_sk(o)	Output skew⁽¹⁾				3	ns
t_sk(pp)	Part-to-part skew⁽²⁾				3	ns

(1) Output skew (t_sk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.

(2) Part-to-part skew (t_sk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits.