SCLS255N December   1995  – February 2024 SN54AHC74 , SN74AHC74

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information — SN74AHC74
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements — VCC = 3.3 V ± 0.3 V
    7. 5.7  Timing Requirements — VCC = 5 V ± 0.5 V
    8. 5.8  Switching Characteristics — VCC = 3.3 V ± 0.5 V
    9. 5.9  Switching Characteristics — VCC = 5 V ± 0.5 V
    10. 5.10 Noise Characteristics
    11. 5.11 Operating Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Considerations
        2. 8.2.1.2 Output Considerations
        3. 8.2.1.3 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • BQA|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4AHC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Device Information
PART NUMBER

RATING

PACKAGE(1)
SN54AHC74

Military

FK (LCCC, 20)
J (CDIP, 14)
W (CFP, 14)
SN74AHC74

Commercial

D (SOIC, 14)
DB (SSOP, 14)
DGV (TVSOP, 14)
N (PDIP, 14)
NS (SO, 14)
PW (TSSOP, 14)
RGY (VQFN, 14)

BQA (WQFN, 14)

(1) For more information, see Section 11.
GUID-3895B2EA-63FB-45CA-BB6D-62CDA7E36111-low.gifLogic Diagram (Positive Logic)