SCLS989 November   2023 SN74AHCT165

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Noise Characteristics
    8. 5.8  Timing Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 TTL-Compatible CMOS Inputs
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

Table 7-1 and Table 7-1 list the functional modes of the SN74AHCT165.

Table 7-1 Operating Mode Table
INPUTS(1) FUNCTION
SH/LD CLK CLK INH
L X X Parallel load
H H X No change
H X H No change
H L ↑ Shift(2)
H ↑ L Shift(2)
(1) H = High Voltage Level, L = Low Voltage Level, X = Do Not Care, ↑ = Low to High transition
(2) Shift : Content of each internal register shifts towards serial output QH. Data at SER is shifted into the first register.
Table 7-2 Output Function Table
INTERNAL REGISTERS(1)(2) OUTPUTS(2)
A — G H Q Q
X L L H
X H H L
(1) Internal registers refer to the shift registers inside the device. These values are set by either loading data from the parallel inputs, or by clocking data in from the serial input.
(2) H = High Voltage Level, L = Low Voltage Level, X = Do Not Care