SCLS946 august   2023 SN74HC165B-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, VCC = 2 V
    7. 6.7  Timing Requirements, VCC = 4.5 V
    8. 6.8  Timing Requirements, VCC = 6 V
    9. 6.9  Switching Characteristics, VCC = 2 V
    10. 6.10 Switching Characteristics, VCC = 4.5 V
    11. 6.11 Switching Characteristics, VCC = 6 V
    12. 6.12 Operating Characteristics
    13. 6.13 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Latching Logic
      3. 8.3.3 Clamp Diode Structure
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Power Considerations
      2. 9.2.2 Input Considerations
      3. 9.2.3 Output Considerations
      4. 9.2.4 Detailed Design Procedure
      5. 9.2.5 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74HC165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 6 V VCC operation.

When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74HC165B-EP devices features a clock-inhibit function and a complemented serial output, QH.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
SN74HC165B-EPPW (TSSOP, 16)5 mm × 6.4 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-65FA984D-D6E1-4301-B28B-6F32F9E9C60E-low.gifLogic Diagram (Positive Logic)