SCES629B may 2005 – july 2023 SN74LV125AT
PRODUCTION DATA
- 1
- 1Features
- 2Description
- 3Revision History
- 4Pin Configuration and Functions
- 5Specifications
- 6Parameter Measurement Information
- 7Detailed Description
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
2 Description
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
Package Information
| PART NUMBER | PACKAGE1 | PACKAGE SIZE 2 |
|---|---|---|
| SN74LV125AT | RGY (VQFN, 14) | 3.50 mm x 3.50 mm |
| D (SOIC, 14) | 8.65 mm × 6 mm | |
| NS (SO, 14) | 10.20 mm x 7.8 mm | |
| DB (SSOP, 14) | 6.20 mm x 7.8 mm | |
| PW (TSSOP, 14) | 5.00 mm x 6.4 mm |
(1) For all available packages, see the orderable addendum at the
end of the data sheet.
(2) The package size (length × width)
is a nominal value and includes pins, where applicable.
Simplified Schematic