SCLS737D
September 2013 – March 2024
SN74LV1T00
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Related Products
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Operating Characteristics
6.8
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Clamp Diode Structure
8.3.2
Balanced CMOS Push-Pull Outputs
8.3.3
LVxT Enhanced Input Voltage
8.3.3.1
Down Translation
8.3.3.2
Up Translation
8.4
Device Functional Modes
9
Application and Implementation
9.1
Power Supply Recommendations
9.2
Layout
9.2.1
Layout Guidelines
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCK|5
MPDS025I
DBV|5
MPDS018S
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scls737d_oa
scls737d_pm
1
Features
Single-supply voltage translator at 5.0/3.3/2.5/1.8V V
CC
Operating range of 1.8V to 5.5V
Up translation:
1.2V
1
to 1.8V
1.5V
1
to 2.5V
1.8V
1
to 3.3V
3.3V
1
to 5.0V
Down translation:
5.0V, 3.3V, 2.5V to 1.8V
5.0V, 3.3V to 2.5V
5.0V to 3.3V
Logic output is referenced to V
CC
Output drive
8mA output drive at 5V
7mA output drive at 3.3V
3mA output drive at 1.8V
Characterized up to 50MHz at 3.3V V
CC
5V tolerance on input pins
–40°C to 125°C operating temperature range
Pb-free packages available: SC-70 (DCK)
2 × 2.1 × 0.65mm
Latch-up performance exceeds 250mA order number package body size per JESD 17
Supports standard Logic pinouts
CMOS output B compatible with AUP1G and LVC1G families
Refer to the V
IH
/V
IL
and output drive for lower V
CC
condition.