SCLS741C November   2013  – October 2023 SN74LV1T32

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 5
  6. 5 Related Products
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Operating Characteristics
    8. 7.8 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Clamp Diode Structure
      2. 9.3.2 Balanced CMOS Push-Pull Outputs
      3. 9.3.3 LVxT Enhanced Input Voltage
        1. 9.3.3.1 Down Translation
        2. 9.3.3.2 Up Translation
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Power Supply Recommendations
    2. 10.2 Layout
      1. 10.2.1 Layout Guidelines
        1. 10.2.1.1 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support (Analog)
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single-supply voltage translator at 5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating range of 1.8 V to 5.5 V
  • Up translation:
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down translation:
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic output is referenced to VCC
  • Output drive:
    • 8 mA output drive at 5 V
    • 7 mA output drive at 3.3 V
    • 3 mA output drive at 1.8 V
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5V Tolerance on input pins
  • –40°C to 125°C operating temperature range
  • Pb-free packages available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm (height 1.1 mm)
  • Latch-up performance exceeds 250 mA
    per JESD 17
  • Supports standard logic pinouts
  • CMOS output B compatible with AUP1G and LVC1G families (1)
1. Refer to the VIH/VIL and output drive for lower VCC condition.