SLLS040I August   1987  – January 2023 SN65ALS176 , SN75ALS176 , SN75ALS176A , SN75ALS176B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Thermal Information
    4. 5.4  Electrical Characteristics - Driver
    5. 5.5  Switching Characteristics - Driver
    6. 5.6  Switching Characteristics - Driver
    7. 5.7  Symbol Equivalents
    8. 5.8  Electrical Characteristics - Receiver
    9. 5.9  Switching Characteristics - Receiver
    10. 5.10 Switching Characteristics - Receiver
    11. 5.11 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

GUID-20220713-SS0I-V976-XGPV-JFJ5MHXW30DJ-low.png Figure 6-1 Driver VOD2 and VOC
GUID-20220713-SS0I-QLCJ-XWFZ-RVZRXV0HVC7P-low.png Figure 6-2 Driver VOD3
GUID-20220713-SS0I-GRXQ-D5PK-B3FSDNHSPCF6-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 6-3 Driver Test Circuit and Voltage Waveforms
GUID-20220713-SS0I-CN2H-XR2R-XDF827WFRR51-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 6-4 Driver Test Circuit and Voltage Waveforms
GUID-20220713-SS0I-FX4D-DZV6-XPZ9WV4KHVBG-low.png Figure 6-5 Driver Test Circuit and Voltage Waveforms
GUID-20220713-SS0I-LNTH-LB2X-KQZ95XW63FWJ-low.png Figure 6-6 Receiver VOH and VOL Test Circuit
GUID-20220713-SS0I-LBFG-F83T-GDFPG5BZBNCT-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
C. tpd = tPLH or tPHL.
Figure 6-7 Receiver Test Circuit and Voltage Waveforms
GUID-20220713-SS0I-6WHL-DFHT-9KNDNDNBCVMZ-low.png
A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
Figure 6-8 Receiver Test Circuit and Voltage Waveforms