SLASF35 January   2024 TAC5312-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Thermal Information
    6. 5.6  Thermal Information
    7. 5.7  Electrical Characteristics
    8. 5.8  Timing Requirements: I2C Interface
    9. 5.9  Switching Characteristics: I2C Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
      2. 6.3.2  Using Multiple Devices With Shared Buses
      3. 6.3.3  Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4  Input Channel Configuration
      5. 6.3.5  Reference Voltage
      6. 6.3.6  Microphone Bias
      7. 6.3.7  Input DC Fault Diagnostics
        1. 6.3.7.1 Fault Conditions
          1. 6.3.7.1.1 Input Pin Short to Ground
          2. 6.3.7.1.2 Input Pin Short to MICBIAS
          3. 6.3.7.1.3 Open Inputs
          4. 6.3.7.1.4 Short Between INxP and INxM
          5. 6.3.7.1.5 Input Pin Overvoltage
          6. 6.3.7.1.6 Input Pin Short to VBAT_IN
        2. 6.3.7.2 Fault Reporting
          1. 6.3.7.2.1 Overcurrent and Overtemperature Protection
      8. 6.3.8  Signal-Chain Processing
        1. 6.3.8.1 ADC Signal-Chain
          1. 6.3.8.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.8.1.2 Programmable Channel Gain Calibration
          3. 6.3.8.1.3 Programmable Channel Phase Calibration
          4. 6.3.8.1.4 Programmable Digital High-Pass Filter
          5. 6.3.8.1.5 Programmable Digital Biquad Filters
          6. 6.3.8.1.6 Programmable Channel Summer and Digital Mixer
          7. 6.3.8.1.7 Configurable Digital Decimation Filters
            1. 6.3.8.1.7.1 Linear Phase Filters
              1. 6.3.8.1.7.1.1 Sampling Rate: 16kHz or 14.7kHz
              2. 6.3.8.1.7.1.2 Sampling Rate: 24kHz or 22.05kHz
              3. 6.3.8.1.7.1.3 Sampling Rate: 32kHz or 29.4kHz
              4. 6.3.8.1.7.1.4 Sampling Rate: 48kHz or 44.1kHz
              5. 6.3.8.1.7.1.5 Sampling Rate: 96kHz or 88.2kHz
              6. 6.3.8.1.7.1.6 Sampling Rate: 384kHz or 352.8kHz
      9. 6.3.9  DAC Signal-Chain
        1. 6.3.9.1 Programmable Channel Gain and Digital Volume Control
        2. 6.3.9.2 Programmable Channel Gain Calibration
        3. 6.3.9.3 Programmable Digital High-Pass Filter
        4. 6.3.9.4 Programmable Digital Biquad Filters
        5. 6.3.9.5 Programmable Digital Mixer
        6. 6.3.9.6 Configurable Digital Interpolation Filters
          1. 6.3.9.6.1 Linear Phase Filters
            1. 6.3.9.6.1.1 Sampling Rate: 16kHz or 14.7kHz
            2. 6.3.9.6.1.2 Sampling Rate: 24kHz or 22.05kHz
            3. 6.3.9.6.1.3 Sampling Rate: 32kHz or 29.4kHz
            4. 6.3.9.6.1.4 Sampling Rate: 48kHz or 44.1kHz
            5. 6.3.9.6.1.5 Sampling Rate: 96kHz or 88.2kHz
            6. 6.3.9.6.1.6 Sampling Rate: 384kHz or 352.8kHz
      10. 6.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
  8. 7 Register Maps
    1. 7.1 Page 0 Registers
    2. 7.2 Page 1 Registers
    3. 7.3 Page_3 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for external HVDD case), fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 x fS, TDM slave mode and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR LINE INPUT RECORDING
Differential input full-scale AC signal voltage AC-coupled input, input fault diagnostic not supported 10 VRMS
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic not supported
Single-ended input full-scale AC signal voltage AC-coupled input, input fault diagnostic not supported 5 VRMS
DC-coupled input, DC common-mode voltage INxP = INxM = 7.1 V, input fault diagnostic not supported
SNR Signal-to-noise ratio, A-weighted(1)(2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 100 dB
IN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 100
IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 90
DR Dynamic range, A-weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 100 dB
IN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 100
IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 96
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –88 TBD dB
IN1 differential DC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –88
IN1 differential DC-coupled input selected and –13-dB full-scale AC signal input, 12-dB channel gain –91
ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING
ADC OTHER PARAMETERS
Input impedance Differential input, between INxP and INxM 66.6 kΩ
Single-ended input, between INxP and INxM 33.3
Offset Shorted Input. TBD mV
Digital volume control range Programmable 0.5-dB steps –120 42 dB
Input Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
>192KSPS 90 kHz
Output data sample rate Programmable 3.675 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 2 Hz
Interchannel isolation –1-dB full-scale AC signal line-in input to non measurement channel –134 dB
Interchannel gain mismatch –6-dB full-scale AC signal line-in input, 0-dB channel gain 0.1 dB
Interchannel phase mismatch 1-kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 92 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 1-VRMS AC input, 1-kHz signal on both pins and measure level at output, CHx_CFG0 D3-2 register bits set to 2b'10 to configure device in high CMRR performance mode 54 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AVSS 20 µVRMS
MICBIAS voltage Programmable 0.5-V steps 3 10 V
MICBIAS current drive MICBIAS voltage 10 V 30 mA
MICBIAS load regulation MICBIAS voltage 10 V, measured up to maximum load 0 1 %
MICBIAS over current protection threshold MICBIAS voltage 10 V 35 mA
INPUT DIAGNOSTICS
Fault monitoring repetition rate Programmable, DC-coupled input 1 4 8 ms
Fault response time Fault monitoring repetition rate 4-ms, DC-coupled input 16 ms
Threshold voltage for (INxx – AVSS) input shorted to ground Programmable 60-mV steps, DC-coupled input 0 900 mV
Threshold voltage for (INxP – INxM) input shorted together Programmable 30-mV steps, DC-coupled input 0 450 mV
Threshold voltage for (MICBIAS – INxx) input shorted to MICBIAS Programmable 30-mV steps, DC-coupled input 0 450 mV
Threshold voltage for (VBAT – INxx) input shorted to VBAT_IN Programmable 30-mV steps, DC-coupled input 0 450 mV
Analog Bypass to Line Out/Head Phone Amplifier
Input impedance Differential input, between INxP and INxM TBD kΩ
Single-ended input, between INxP and INxM TBD
Single Ended Full Scale Output AVDD=3.3V 5 Vrms
Differential Full Scale Output AVDD=3.3V 10 Vrms
Gain Error 0.1 dB
Noise, A-Weighted Idle Channel, Input Shorted to Ground 4 µVRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) Idle Channel, Input Shorted to Ground, AVDD=3.3V 102 dB
THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and -1-dB full-scale AC signal input, 0-dB channel gain TBD dB
DAC Performance for Line Output/Head Phone Playback
Full Scale Output Voltage Differential output between OUTxP and OUTxM, AVDD=3.3V 2 VRMS
Single-ended Output, AVDD=3.3V 1
Pseudo Differential Output between OUTxP and OUTxM, AVDD=3.3V 1
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential Output, 0dBFS Signal, AVDD=3.3V 106 dB
Single Ended Output, 0dBFS Signal, AVDD=3.3V 103
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V 96
Differential Output, 0dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode TBD dB
Single Ended Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode TBD
Pseudo Differential Output, 0dBFS Signal, AVDD=3.3V, Power Tune Mode
DR Dynamic range, A-weighted(2) Differential Output, -60dBFS Signal, AVDD=3.3V 106 dB
Single Ended Output, -60dBFS Signal, AVDD=3.3V 103
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V 96
Differential Output, -60dBFS Signal, AVDD=3.3V, 0dBFS Signal, Power Tune Mode dB
Single Ended Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode
Pseudo Differential Output, -60dBFS Signal, AVDD=3.3V, Power Tune Mode
THD+N Total harmonic distortion(2) –95 dB
Head Phone Load Range 16 Ω
Line Out Load Range 600 Ω
Channel gain control range Programmable 1-dB steps –6 12 dB
DAC Channel OTHER PARAMETERS
Output Offset 0 Input TBD mV
Output Common Mode Common Mode Level for OUTxP and OUTxM AVDD=3.3V (Register Configurable) Common Mode Level for OUTxP and OUTxM AVDD=3.3V 1.625 V
Common Mode Error DC Error in Common Mode Voltage ±10 mV
Digital volume control range Programmable 0.5-dB steps –120 42 dB
Output Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
>192KSPS 90 kHz
Input data sample rate Programmable 7.35 768 kHz
Input data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 2 Hz
Interchannel isolation –134 dB
Interchannel gain mismatch 0.1 dB
Interchannel phase mismatch 1-kHz sinusoidal signal 0.01 Degrees
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 92 dB
Mute Attenuation –130 dB
Pout Output Power Delivery Single ended/Pseudo Differential RL=16 Ohms, THD+N<1% 62.5 mW
Line Out DIAGNOSTICS
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 x IOVDD V
All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 1.8-V operation 0.65 x IOVDD IOVDD + 0.3 V
All digital pins except GPI1A, GPI2A, ADDRA, SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except GPO1A, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except GPO1A, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except GPO1A, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except GPO1A, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(AVDD) Low-level digital input logic voltage threshold For Pins GPI1A, GPI2A, ADDRA –0.3 0.35 x AVDD V
VIH(AVDD) High-level digital input logic voltage threshold For Pins GPI1A, GPI2A, ADDRA 0.65 x AVDD AVDD + 0.3 V
VOL(AVDD) Low-level digital output voltage For GPO1A Pin 0.45 V
VOH(AVDD) High-level digital output voltage For GPO1A Pin AVDD – 0.45 V
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 x IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 x IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD [char_not_recognized] 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in hardware shutdown mode SHDNZ = 0, all device external clocks stopped 0.5 µA
IBSTVDD, or IHVDD 0.1
IIOVDD 0.1
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped TBD µA
IBSTVDD, or IHVDD 0.1
IIOVDD 0.1
IAVDD Current consumption when MICBIAS ON, MICBIAS voltage 10 V, 30 mA load, ADC off fS = 48 kHz, BCLK = 256 [char_not_recognized] fS TBD mA
IBSTVDD TBD
IHVDD TBD
IIOVDD 0.01
IAVDD Current consumption with ADC 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 [char_not_recognized] fS TBD mA
IBSTVDD, or IHVDD 0
IIOVDD 0.1
IAVDD Current consumption with ADC 2-channel operation at fS 48-kHz, MICBIAS on, PLL off, BCLK = 512 [char_not_recognized] fS TBD mA
IBSTVDD, or IHVDD 0
IIOVDD 0.1
IAVDD Current consumption with DAC to HP 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 [char_not_recognized] fS TBD mA
IBSTVDD, or IHVDD 0
IIOVDD 0.2
IAVDD Current consumption with DAC to HP 2-channel operation at fS 48-kHz, MICBIAS off, PLL off, BCLK = 512 [char_not_recognized] fS TBD mA
IBSTVDD, or IHVDD 0
IIOVDD TBD
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.