SLASF31 December   2023 TAD5242

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 6.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Analog Output Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 DAC Signal-Chain
        1. 8.3.6.1 Configurable Digital Interpolation Filters
          1. 8.3.6.1.1 Linear Phase Filters
            1. 8.3.6.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
  11. 10Power Supply Recommendations
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.1 Active Mode

The device wakes up in active mode when AVDD and IOVDD are available. Configure all hardware control pins (MD0, MD1, MD2, MD3, MD4,MD5 and MD6) for the device desired mode of operation before enabling clocks for the device.

In active mode, when the audio clocks are available, the device automatically powers up all DAC channels and starts transmitting and playing data over the audio serial interface. If the clocks are stopped, then the device auto powers down the DAC channels.