SLOS903B May   2015  – February 2016 TAS5720L , TAS5720M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable I2C Address
      2. 7.3.2 I2C Interface
        1. 7.3.2.1 Writing to the I2C Interface
        2. 7.3.2.2 Reading from the I2C Interface
      3. 7.3.3 Serial Audio Interface (SAIF)
        1. 7.3.3.1 Stereo I2S Format Timing
        2. 7.3.3.2 Stereo Left-Justified Format Timing
        3. 7.3.3.3 Stereo Right-Justified Format Timing
        4. 7.3.3.4 TDM Format Timing
      4. 7.3.4 Audio Signal Path
        1. 7.3.4.1 High-Pass Filter (HPF)
        2. 7.3.4.2 Amplifier Analog Gain and Digital Volume Control
        3. 7.3.4.3 Digital Clipper
        4. 7.3.4.4 Class-D Amplifier Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SDZ)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Mute Mode
      5. 7.4.5 Faults and Status
    5. 7.5 Register Maps
      1. 7.5.1 Device Identification
      2. 7.5.2 Power Control Register
      3. 7.5.3 Digital Control Register 1
      4. 7.5.4 Digital Control Register 2
      5. 7.5.5 Volume Control Register
      6. 7.5.6 Analog Control Register
      7. 7.5.7 Fault Configuration and Error Status Register
      8. 7.5.8 Digital Clipper 2
      9. 7.5.9 Digital Clipper 1
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Procedure
        1. 8.2.2.1 Overview
        2. 8.2.2.2 Select the PWM Frequency
        3. 8.2.2.3 Select the Amplifier Gain and Digital Volume Control
        4. 8.2.2.4 Select Input Capacitance
        5. 8.2.2.5 Select Decoupling Capacitors
        6. 8.2.2.6 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage(2) PVDD, AVDD (TAS5720L) –0.3 20 V
PVDD, AVDD (TAS5720M) –0.3 30
DVDD –0.3 4
Digital input voltage Digital inputs referenced to DVDD supply –0.5 VDVDD + 0.5 V
Ambient operating temperature, TA –25 85 °C
Storage temperature, Tstg –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
(2) All voltages are with respect to network ground pin.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
PVDD/
AVDD		 Power supply voltage TAS5720L 4.5 16.5 V
TAS5720M 4.5 26.4 V
DVDD Power supply voltage 3 3.3 3.6 V
VIH(DR) High-level digital input voltage VDVDD V
VIL(DR) Low-level digital input voltage 0 V
RSPK Minimum speaker load 3.2 Ω
TA Operating free-air temperature –25 85 °C
TJ Operating junction temperature –25 150 °C

6.4 Thermal Information

THERMAL METRIC(1) TAS5720x UNIT
RSM (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 37.3 °C/W
RθJCtop Junction-to-case (top) thermal resistance 30.4 °C/W
RθJB Junction-to-board thermal resistance 7.9 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 7.7 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1, Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction filter at the device output.
PARAMETER CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUT AND OUTPUT
VIH High-level digital input logic voltage threshold All digital pins 70% VDVDD
VIL Low-level digital input logic voltage threshold All digital pins 30% VDVDD
IIH Input logic "high" leakage for digital inputs All digital pins, excluding SDZ 15 µA
IIL Input logic "low" leakage for digital inputs All digital pins, excluding SDZ –15 µA
IIH(SDZ) Input logic "high" leakage for SDZ inputs SDZ 1 µA
IIL(SDZ) Input logic "low" leakage for SDZ inputs SDZ –1 µA
VOL Output logic "low" for FAULTZ open drain Output IOL = –2 mA 10% VDVDD
CIN Input capacitance for digital inputs All digital pins 5 pF
MASTER CLOCK
D(MCLK) Allowable MCLK duty cycle 45% 50% 55%
f(MCLK) MCLK input frequency 25 MHz
Supported single-speed MCLK frequencies Values: 64, 128, 256, and 512 64 × fS 512 × fS
Supported double-speed MCLK frequencies Values: 64, 128, and 256 64 × fS 256 × fS
SERIAL AUDIO PORT
D(BCLK) Allowable BCLK duty cycle 45% 50% 55%
f(BCLK) BCLK input frequency 25 MHz
Supported single-speed BCLK frequencies Values: 64, 128, 256, and 512 64 × fS 512 × fS
Supported double-speed BCLK frequencies Values: 64, 128, and 256 64 × fS 256 × fS
fS Supported single-speed input sample rates Values: 44.1 and 48 44.1 48 kHz
Supported double-speed input sample rates Values: 88.2 and 96 88.2 96 kHz
I2C CONTROL PORT
CL(I2C) Allowable load capacitance for each I2C Line 400 pF
fSCL SCL frequency No wait states 400 kHz
PROTECTION
OTE(THRESH) Overtemperature error (OTE) threshold 150 °C
OTE(HYST) Overtemperature error (OTE) hysteresis 15 °C
OCE(THRESH) Overcurrent error (OCE) threshold V(PVDD) = 16.5 V, TA = 25°C 6 A
DCE(THRESH) DC error (DCE) threshold V(PVDD) = 16.5 V, TA = 25°C 2.6 V
AMPLIFIER PERFORMANCE
POUT Continuous average power RL= 4 Ω, 10% THD+N, V(PVDD) = 7.2 V,
fIN = 1 kHz		 6.6 W
RL= 8 Ω, 10% THD+N, V(PVDD) = 7.2 V,
fIN = 1 kHz		 3.7
RL= 4 Ω, 10% THD+N, V(PVDD) = 12 V,
fIN = 1 kHz		 17.8
RL= 8 Ω, 10% THD+N, V(PVDD) = 12 V,
fIN = 1 kHz		 10.1
RL= 4 Ω, 10% THD+N, V(PVDD) = 15 V,
fIN = 1 kHz, TA= 60°C 		27.4
RL= 8 Ω, 10% THD+N, V(PVDD) = 15 V,
fIN = 1 kHz		 15.8
RL= 4 Ω, 10% THD+N, V(PVDD) = 19 V,
fIN = 1 kHz		 27
RL= 8 Ω, 10% THD+N, V(PVDD) = 19 V,
fIN = 1 kHz		 25.3
RL= 4 Ω, 10% THD+N, V(PVDD) = 24 V,
fIN = 1 kHz		 22.1
RL= 8 Ω, 10% THD+N, V(PVDD) = 24 V,
fIN = 1 kHz		 39.8
THD+N Total harmonic distortion plus noise RL= 4 Ω,V(PVDD) = 7.2 V, POUT = 1 W,
fIN = 1 kHz		 0.033%
RL= 8 Ω,V(PVDD) = 7.2 V, POUT = 1 W,
fIN = 1 kHz		 0.015%
RL= 4 Ω, V(PVDD)= 12 V, POUT = 1 W,
fIN = 1 kHz		 0.03%
RL= 8 Ω, V(PVDD)= 12 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz		 0.013v
RL= 4 Ω, V(PVDD) = 15 V, POUT = 1 W,
20 Hz ≤ fIN≤ 20 kHz		 0.028%
RL= 8 Ω, V(PVDD) = 15 V, POUT = 1 W,
20 Hz ≤ fIN≤ 20 kHz		 0.012%
RL= 4 Ω, V(PVDD) = 19 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz		 0.026%
RL= 8 Ω, V(PVDD) = 19 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz		 0.013%
RL= 4 Ω, V(PVDD) = 24 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz		 0.026%
RL= 8 Ω, V(PVDD) = 24 V, POUT = 1 W,
20 Hz ≤ fIN ≤ 20 kHz		 0.016%
PEFF Power efficiency RL= 8 Ω, V(PVDD) = 12 V, POUT = 9 W 91%
RL= 8 Ω, V(PVDD) = 12 V, POUT = 9 W; fPWM = 384 kHz 90%
RL= 8 Ω, V(PVDD) = 24 V, POUT = 40 W 90%
VN Integrated noise floor voltage A-Weighted,RL= 8 Ω, Gain = 20.7 dBV 50 µVrms
φCC Channel-to-channel phase shift Output phase shift between multiple devices from 20 Hz to 20 kHz. Across all sample frequencies and SAIF operating modes. 0.2 deg
A(RIPPLE) Frequency response Maximum deviation above or below passband gain. ±0.15 dB
-3 dB Output Cutoff Frequency 0.47 × fS Hz
AV(00) Amplifier analog gain(1) ANALOG_GAIN[1:0] register bits set to "00" 19.2 dBV
AV(01) ANALOG_GAIN[1:0] register bits set to "01" 20.7
AV(10) ANALOG_GAIN[1:0] register bits set to "10" 23.5
AV(11) ANALOG_GAIN[1:0] register bits set to "11" 26.3
AV(ERROR) Amplifier analog gain error ±0.15 dB
VOS DC output offset voltage Measured between OUTP and OUTN 1.5 mV
KCP Click-pop performance –60 dBV
PSRR Power supply rejection ratio DC, 5.5 V ≤ V(PVDD) ≤ 26.4 V 87 dB
AC, V(PVDD)= 16.5 V + 100 mVP-P, f(RIPPLE) from 20 Hz to 10 kHz 53
AC, V(PVDD)= 16.5 V + 100 mVP-P, f(RIPPLE) from 10 Hz to 20 kHz 50
RDS(on)FET Power stage FET on-resistance TA = 25°C 120 mΩ
RDS(on)TOT Power stage total on-resistance (FET+bond+package) TA = 25°C 150 mΩ
IPK Peak output current TA = 25°C 5 A
f(HP) –3 dB high-pass filter corner frequency f = 44.1 kHz 3.675 Hz
f = 48 kHz 4
f = 88.2 kHz 7.35
f = 96 kHz 8
f(PWM) PWM switching frequency Values: 6, 8, 10, 12, 14, 16, 20, and 24 6 24 fS
(1) When PVDD is less than 5.5 V, the voltage regulator that operates the analog circuitry does not have enough headroom to maintain the nominal 5.4-V internal voltage. The lack of headroom causes a direct reduction in gain (approximately –0.8 dB at 5 V and –1.74 dB at 4.5 V), but the device functions properly down to VPVDD = 4.5 V.

6.6 Timing Requirements

MIN NOM MAX UNIT
tACTIVE Shutdown to Active Time From deassertion of SDZ (both pin and I2C register bit) until the Class-D amplifier begins switching. 25 ms
tWAKE Wake Time From the deassertion of SLEEP until the Class-D amplifier starts switching. 1
tSLEEP Sleep Time From the assertion of SLEEP until the Class-D amplifier stops switching. tvrmp + 1
tMUTE Play to Mute Time From the assertion of MUTE mode until the volume has ramped to the minimum. tvrmp
tPLAY Un-Mute to Play Time From the deassertion of MUTE until the volume has returned to its current setting. tvrmp
tSD Active to Shutdown Time From the assertion of SDZ (pin or I2C register bit) until the Class-D amplifier stops switching. tvrmp + 1
SERIAL AUDIO PORT
tH_L Time high and low, BCLK, LRCLK, SDIN inputs 10 ns
tSU
tHLD 		Setup and hold time. LRCLK, SDIN input to BCLK edge. Input tRISE ≤ 1 ns, input tFALL ≤ 1 ns 5 ns
Input tRISE ≤ 4 ns, input tFALL ≤ 4 ns 8
Input tRISE ≤ 8 ns, input tFALL ≤ 8 ns 12
tRISE Rise-time BCLK, LRCLK, SDIN inputs 8 ns
tFALL Fall-time BCLK, LRCLK, SDIN inputs 8
I2C CONTROL PORT
tBUS Bus free time between start and stop conditions 1.3 µs
tHOLD1(I2C) Hold Time, SCL to SDA 80 ns
tHOLD2(I2C) Hold Time, start condition to SCL 0.6 µs
tSTART(I2C) I2C Startup Time after DVDD Power On Reset 12 ms
tRISE(I2C) Rise Time, SCL and SDA 300 ns
tFALL(I2C) Fall Time, SCL and SDA 300 ns
tSU1(I2C) Setup, SDA to SCL 100 ns
tSU2(I2C) Setup, SCL to start condition 0.6 µs
tSU3(I2C) Setup, SCL to stop condition 0.6 µs
tW(H) Required pulse duration, SCL "HIGH" 0.6 µs
tW(L) Required pulse duration, SCL "LOW" 1.3 µs
PROTECTION
tFAULTZ Amplifier fault time-out period DC detect error 650 ms
OTE or OCE fault 1.3 s
TAS5720L TAS5720M setup_hold_times_slos903.gif Figure 1. SAIF Timing
TAS5720L TAS5720M t0027-01.gif Figure 2. SCL and SDA Timing
TAS5720L TAS5720M t0028-01.gif Figure 3. Start and Stop Conditions Timing

When SDZ is deasserted (and the device is not in sleep mode), the amplifier begins to switch after a period of tACTIVE. At this point, the volume ramps from –100 dB to the programmed digital volume control (DVC) setting at a rate of 0.5 dB every eight sample periods. Ramping the volume prevents audible artifacts that can occur if discontinuous volume changes are applied while audio is being played back. This period, tVRMP, depends on the DVC setting and sample rate. Typical values for tVRMP for a DVC of 0 dB are shown in Timing Requirements. Figure 4 illustrates mode timing.

The time to enter or exit sleep or mute and the time to enter shudown are dominated by tVRMP. Table 1 lists the timing parameters based on tVRMP.

TAS5720L TAS5720M mode_timing_slos852.gif Figure 4. Mode Timing

Table 1. Typical DVC Ramp Times

SAMPLE
RATE (kHZ)		 RAMP TIMES (tVRAMP)
FROM –100 dB to 0 dB (ms)
44.1 36.3
48 33.3
88.2 18.1
96 16.7

6.7 Typical Characteristics

TA = 25ºC, V(PVDD) = 15 V, V(DVDD) = 3.3 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, f(PWM) = 768 kHz, Gain = 20.7 dBV, SDZ = 1, Measured with an Audio Precision SYS-2722 High-Performance Audio Analyzer and using a 15-µH, 0.68-µF reconstruction filter at the device output.
TAS5720L TAS5720M D002_SLOS903.gif
V(PVDD) = 7.2 V POUT = 1 W f(PWM) = 384 kHz
Figure 5. THD+N vs Frequency
TAS5720L TAS5720M D004_SLOS903.gif
V(PVDD) = 12 V POUT = 1 W f(PWM) = 384 kHz
Figure 7. THD+N vs Frequency
TAS5720L TAS5720M D006_SLOS903.gif
V(PVDD) = 15 V POUT = 1 W f(PWM) = 384 kHz
Figure 9. THD+N vs Frequency
TAS5720L TAS5720M D008_SLOS903.gif
V(PVDD) = 19 V POUT = 1 W f(PWM) = 384 kHz
Figure 11. THD+N vs Frequency
TAS5720L TAS5720M D010_SLOS903.gif
V(PVDD) = 24 V POUT = 1 W f(PWM) = 384 kHz
Figure 13. THD+N vs Frequency
TAS5720L TAS5720M D012_SLOS903.gif
V(PVDD) = 7.2 V f(PWM) = 384 kHz
Figure 15. THD+N vs Output Power
TAS5720L TAS5720M D014_SLOS903.gif
V(PVDD) = 12 V f(PWM) = 384 kHz
Figure 17. THD+N vs Output Power
TAS5720L TAS5720M D016_SLOS903.gif
V(PVDD) = 15 V f(PWM) = 384 kHz
Figure 19. THD+N vs Output Power
TAS5720L TAS5720M D018_SLOS903.gif
V(PVDD) = 19 V f(PWM) = 384 kHz
Figure 21. THD+N vs Output Power
TAS5720L TAS5720M D020_SLOS903.gif
V(PVDD) = 24 V f(PWM) = 384 kHz
Figure 23. THD+N vs Output Power
TAS5720L TAS5720M D022_SLOS903.gif
Analog Gain = Setting 11 f(PWM) = 384 kHz
Figure 25. Output Power vs Supply Voltage
TAS5720L TAS5720M D024_SLOS903.gif
f(PWM) = 384 kHz
Figure 27. A-Weighted Idle Channel Noise vs Supply Voltage
TAS5720L TAS5720M D026_SLOS903.gif
RL = 4 Ω f(PWM) = 384 kHz
Figure 29. Efficiency vs Output Power
TAS5720L TAS5720M D028_SLOS903.gif
RL = 8 Ω f(PWM) = 384 kHz
Figure 31. Efficiency vs Output Power
TAS5720L TAS5720M D030_SLOS903.gif
f(PWM) = 384 kHz
Figure 33. PVDD PSRR vs Frequency
TAS5720L TAS5720M D032_SLOS903.gif
f(PWM) = 384 kHz
Figure 35. DVDD PSRR vs Frequency
TAS5720L TAS5720M D034_SLOS903.gif
Figure 37. Supply Idle Current vs PVDD
TAS5720L TAS5720M D003_SLOS903.gif
V(PVDD) = 7.2 V POUT = 1 W
Figure 6. THD+N vs Frequency
TAS5720L TAS5720M D005_SLOS903.gif
V(PVDD) = 12 V POUT = 1 W
Figure 8. THD+N vs Frequency
TAS5720L TAS5720M D007_SLOS903.gif
V(PVDD) = 15 V POUT = 1 W
Figure 10. THD+N vs Frequency
TAS5720L TAS5720M D009_SLOS903.gif
V(PVDD) = 19 V POUT = 1 W
Figure 12. THD+N vs Frequency
TAS5720L TAS5720M D011_SLOS903.gif
V(PVDD) = 24 V POUT = 1 W
Figure 14. THD+N vs Frequency
TAS5720L TAS5720M D013_SLOS903.gif
V(PVDD) = 7.2 V
Figure 16. THD+N vs Output Power
TAS5720L TAS5720M D015_SLOS903.gif
V(PVDD) = 12 V
Figure 18. THD+N vs Output Power
TAS5720L TAS5720M D017_SLOS903.gif
V(PVDD) = 15 V
Figure 20. THD+N vs Output Power
TAS5720L TAS5720M D019_SLOS903.gif
V(PVDD) = 19 V
Figure 22. THD+N vs Output Power
TAS5720L TAS5720M D021_SLOS903.gif
V(PVDD) = 24 V Gain = 20.7 dBV
Figure 24. THD+N vs Output Power
TAS5720L TAS5720M D023_SLOS903.gif
Analog Gain = Setting 11
Figure 26. Output Power vs Supply Voltage
TAS5720L TAS5720M D025_SLOS903.gif
Figure 28. Efficiency vs Output Power
TAS5720L TAS5720M D027_SLOS903.gif
RL = 4 Ω
Figure 30. Efficiency vs Output Power
TAS5720L TAS5720M D029_SLOS903.gif
RL = 8 Ω
Figure 32. Efficiency vs Output Power
TAS5720L TAS5720M D031_SLOS903.gif
Figure 34. PVDD PSRR vs Frequency
TAS5720L TAS5720M D033_SLOS903.gif
Figure 36. DVDD PSRR vs Frequency
TAS5720L TAS5720M D035_SLOS903.gif
Figure 38. Shutdown Current vs PVDD