SLASEV8 December   2020 TAS5822M

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
      1. 6.7.1 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
      2. 6.7.2 Parallel Bridge Tied Load (PBTL) Configuration Curves with 1SPW Modulation, Fsw = 768kHz
    8. 6.8 Parametric Measurement Information
      1. 6.8.1 Power Consumption Summary
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Minimize EMI with Spread Spectrum
      4. 7.4.4 Minimize EMI with channel to channel phase shift
      5. 7.4.5 Minimize EMI with Multi-Devices PWM Phase Synchronization
      6. 7.4.6 Thermal Foldback
      7. 7.4.7 Device State Control
      8. 7.4.8 Device Modulation
        1. 7.4.8.1 BD Modulation
        2. 7.4.8.2 1SPW Modulation
        3. 7.4.8.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Slave Address
        1. 7.5.2.1 Random Write
        2. 7.5.2.2 Sequential Write
        3. 7.5.2.3 Random Read
        4. 7.5.2.4 Sequential Read
        5. 7.5.2.5 DSP Memory Book, Page and BQ update
        6. 7.5.2.6 Example Use
        7. 7.5.2.7 Checksum
          1. 7.5.2.7.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.2.7.2 Exclusive or (XOR) Checksum
      3. 7.5.3 Control via Software
        1. 7.5.3.1 Startup Procedures
        2. 7.5.3.2 Shutdown Procedures
        3. 7.5.3.3 Protection and Monitoring
          1. 7.5.3.3.1 Over current Shutdown (OCSD)
          2. 7.5.3.3.2 Speaker DC Protection
          3. 7.5.3.3.3 Device Over Temperature Protection
          4. 7.5.3.3.4 Over Voltage Protection
          5. 7.5.3.3.5 Under Voltage Protection
          6. 7.5.3.3.6 Clock Fault
    6. 7.6 Register Maps
      1. 7.6.1 CONTROL PORT Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 2.0 (Stereo BTL) System
      2. 8.2.2 MONO （PBTL) System
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Bootstrap Capacitors
          2. 8.2.2.2.2 Inductor Selections
          3. 8.2.2.2.3 Power Supply Decoupling
          4. 8.2.2.2.4 Output EMI Filtering
        3. 8.2.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
    1. 9.1 DVDD Supply
    2. 9.2 PVDD Supply
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Guidelines for Audio Amplifiers
      2. 10.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 10.1.3 Optimizing Thermal Performance
        1. 10.1.3.1 Device, Copper, and Component Layout
        2. 10.1.3.2 Stencil Pattern
          1. 10.1.3.2.1 PCB footprint and Via Arrangement
          2. 10.1.3.2.2 Solder Stencil
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-4744ADF7-CBB5-4D5A-A6BB-12DC5CD290A2-low.gifFigure 5-1 DCP Package,38-Pin TSSOP, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
DGND 8,12 G Digital ground
DVDD 9 P 3.3-V or 1.8-V digital power supply
VR_DIG 11 P Internally regulated 1.5-V digital supply voltage. This pin must not be used to drive external devices
ADR/ FAULT 10 DIO Different I2 C device address can be set by selecting different pull up resistor to DVDD, see Table 4 for details. This pin can be programed by writing 1 to a register bit after Power up bit. In this mode, the ADR/ FAULT Is redefined as FAULT,go to Page 0, Book 0, set register 0x61 = 0x0b first, then set register 0x60 = 0x01
LRCLK 13 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
SCLK 14 DI Bit clock for the digital signal that is active on the input data line of the serial data port.
SDIN 15 DI Data line to the serial data port
SDOUT 26 DO Serial Audio data output, the source data can select as Pre-DSP or Post DSP
SDA 27 DI/O I2C serial control data interface input/output
SCL 28 DI I2C serial control clock input
PDN 29 DI Power Down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
AVDD 30 P Internally regulated 5-V analog supply voltage. This pin must not be used to drive external devices
AGND 31 G Analog ground
PVDD 6 P PVDD voltage input
7 P
32 P
33 P
PGND 3 G Ground reference for power device circuitry. Connect this pin to system ground.
36 G
OUT_A+ 5 O Positive pin for differential speaker amplifier output A+
BST_A+ 4 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+
OUT_A- 2 O Negative pin for differential speaker amplifier output A-
BST_A- 1 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-
BST_B- 38 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-
OUT_B- 37 O Negative pin for differential speaker amplifier output B
BST_B+ 35 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+
OUT_B+ 34 O Positive pin for differential speaker amplifier output B+
NC 18 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 19 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 20 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 21 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 17 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 16 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 22 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 25 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 23 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
NC 24 - No Connect Pin. Can be shorted to PVDD or shorted to GND or left open.
PowerPAD™ G Connect to the system Ground
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), P = Power, G = Ground (0 V)