SLLSFP9 February   2024 TCAN1465-Q1 , TCAN1469-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCC Pin
      4. 8.3.4  GND
      5. 8.3.5  INH/LIMP Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  TXD Pin
      8. 8.3.8  RXD Pin
      9. 8.3.9  SDO or nINT Interrupt Pin
      10. 8.3.10 nCS Pin
      11. 8.3.11 SCK
      12. 8.3.12 SDI
      13. 8.3.13 CANH and CANL Bus Pins
      14. 8.3.14 CAN FD SIC Transceiver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Listen Only Mode
      4. 8.4.4 Sleep Mode
        1. 8.4.4.1 Bus Wake via RXD Request (BWRR) in Sleep Mode
        2. 8.4.4.2 Local Wake Up (LWU) via WAKE Input Terminal
      5. 8.4.5 Selective Wake-up
        1. 8.4.5.1 Selective Wake Mode
        2. 8.4.5.2 Frame Detection
        3. 8.4.5.3 Wake-Up Frame (WUF) Validation
        4. 8.4.5.4 WUF ID Validation
        5. 8.4.5.5 WUF DLC Validation
        6. 8.4.5.6 WUF Data Validation
        7. 8.4.5.7 Frame error counter
        8. 8.4.5.8 CAN FD Frame Tolerance
      6. 8.4.6 Fail-safe Features
        1. 8.4.6.1 Sleep Mode via Sleep Wake Error
        2. 8.4.6.2 Fail-safe Mode
      7. 8.4.7 Protection Features
        1. 8.4.7.1 Driver and Receiver Function
        2. 8.4.7.2 Floating Terminals
        3. 8.4.7.3 TXD Dominant Time Out (DTO)
        4. 8.4.7.4 CAN Bus Short Circuit Current Limiting
        5. 8.4.7.5 Thermal Shutdown
        6. 8.4.7.6 Under-Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.7.6.1 UVSUP, UVCC
          2. 8.4.7.6.2 UVIO
            1. 8.4.7.6.2.1 Fault Behavior
        7. 8.4.7.7 Watchdog (TCAN1469-Q1)
          1. 8.4.7.7.1 Watchdog Error Counter
          2. 8.4.7.7.2 Watchdog SPI Control Programming
            1. 8.4.7.7.2.1 Watchdog Configuration Registers Lock and Unlock
          3. 8.4.7.7.3 Watchdog Timing
          4. 8.4.7.7.4 Question and Answer Watchdog
            1. 8.4.7.7.4.1 WD Question and Answer Basic Information
            2. 8.4.7.7.4.2 Question and Answer Register and Settings
            3. 8.4.7.7.4.3 WD Question and Answer Value Generation
              1. 8.4.7.7.4.3.1 Answer Comparison
              2. 8.4.7.7.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.7.7.4.4 Question and Answer WD Example
              1. 8.4.7.7.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.7.7.4.4.2 Example of Performing a Question and Answer Sequence
      8. 8.4.8 Bus Fault Detection and Communication (TCAN1469-Q1)
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCK):
        3. 8.5.1.3 SPI Serial Data Input (SDI):
        4. 8.5.1.4 SPI Serial Data Output (SDO):
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Signal Improvement Capable (SIC)
      2. 9.1.2 CAN Termination
        1. 9.1.2.1 Termination
        2. 9.1.2.2 CAN Bus Biasing
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1 Brownout
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Registers
    1. 10.1 Register Maps
      1. 10.1.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = value]
      2. 10.1.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 10.1.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
      4. 10.1.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
      5. 10.1.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
      6. 10.1.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
      7. 10.1.7  WAKE_PIN_CONFIG Register (Address = 11h) [reset = 4h]
      8. 10.1.8  PIN_CONFIG Register (Address = 12h) [reset = 00h]
      9. 10.1.9  WD_CONFIG_1 Register (Address = 13h) [reset = 15h]
      10. 10.1.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 10.1.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      12. 10.1.12 WD_RST_PULSE Register (Address = 16h) [reset = 07h]
      13. 10.1.13 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      14. 10.1.14 FSM_CNTR Register (Address = 18h) [reset = 00h]
      15. 10.1.15 DEVICE_RST Register (Address = 19h) [reset = 00h]
      16. 10.1.16 DEVICE_CONFIG1 Register (Address = 1Ah) [reset = 00h]
      17. 10.1.17 DEVICE_CONFIG2 Register (Address = 1Bh) [reset = 0h]
      18. 10.1.18 SWE_EN Register (Address 1Ch) [reset = 04h]
      19. 10.1.19 SDO_CONFIG Register (Address = 29h) [reset = 00h]
      20. 10.1.20 WD_QA_CONFIG Register (Address = 2Dh) [reset = 00h]
      21. 10.1.21 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      22. 10.1.22 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      23. 10.1.23 SW_ID1 Register (Address = 30h) [reset = 00h]
      24. 10.1.24 SW_ID2 Register (Address = 31h) [reset = 00h]
      25. 10.1.25 SW_ID3 Register (Address = 32h) [reset = 00h]
      26. 10.1.26 SW_ID4 Register (Address = 33h) [reset = 00h]
      27. 10.1.27 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      28. 10.1.28 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      29. 10.1.29 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      30. 10.1.30 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      31. 10.1.31 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      32. 10.1.32 DATA_y Register (Address = 39h + formula) [reset = 00h]
      33. 10.1.33 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      34. 10.1.34 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      35. 10.1.35 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      36. 10.1.36 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      37. 10.1.37 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      38. 10.1.38 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      39. 10.1.39 DEVICE_CONFIGx Register (Address = 4Bh) [reset = 0h]
      40. 10.1.40 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      41. 10.1.41 INT_1 Register (Address = 51h) [reset = 00h]
      42. 10.1.42 INT_2 Register (Address = 52h) [reset = 40h]
      43. 10.1.43 INT_3 Register (Address 53h) [reset = 00h]
      44. 10.1.44 INT_CANBUS Register (Address = 54h) [reset = 00h]
      45. 10.1.45 INT_GLOBAL_ENABLE (Address = 55h) [reset = 00h]
      46. 10.1.46 INT_ENABLE_1 Register (Address = 56h) [reset = FFh]
      47. 10.1.47 INT_ENABLE_2 Register (Address = 57h) [reset = 1Fh]
      48. 10.1.48 INT_ENABLE_3 Register (Address = 58h) [reset = 0h]
      49. 10.1.49 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
      50. 10.1.50 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 EMC Requirements:
      3. 11.1.3 Conformance Test Requirements:
      4. 11.1.4 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Switching Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN TRANSCEIVER SWITCHING CHARACTERISTICS
tprop(TxD-busdom)
Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant)
45Ω ≤ RL ≤ 65Ω, CL = 100pF, RCM = open; see Figure 9-4; V; The input signal on TXD shall have rising times (10% to 90%) and fall times (90% to 10%) of less than 10ns		 80 ns
tprop(TxD-busrec) Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive) 80 ns
tsk(p) Pulse skew (|tpHR – tpLD|) 10 40 ns
tR/F Differential output signal rise time 5 55 75 ns
tprop(busdom-RxD) Propagation delay time, bus dominant input to RxD low output
CL(RXD) = 15pF;
see Figure 9-5 ; The input signal on TXD shall have rising times (10% to 90%) and fall times (90% to 10%) of less than 10ns		 110 ns
tprop(busrec-RxD) Propagation delay time, bus to recessive input to RXD high output 110 ns
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD) dominant to recessive 45Ω ≤ RL ≤ 65Ω, CL = 100pF, CL(RXD) = 15pF 
See Figure 9-6		 100 190 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD) recessive to dominant 45Ω ≤ RL ≤ 65Ω, CL = 100pF, CL(RXD) = 15pF 
See Figure 9-6		 110 190 ns
CAN FD BIT TIMING
SIGNAL IMPROVEMENT CHARACTERISTICS
tPAS_REC_START Signal improvement start time of passive recessive phase Measured from rising TXD edge with < 5ns slope at 50% threshold, to the end of the signal improvement phase;
RDIFF_PAS_REC ≥ MIN RDIFF_ACT_REC;
RSE_CANH/L ≥ MIN RSE_SIC_REC
See Figure 9-6		 530 ns
tACT_REC_START Start time of active signal improvement phase Measured from rising TXD edge with < 5ns slope at 50% threshold, 120 ns
tACT_REC_END End time of active signal improvement phase Measured from rising TXD edge with < 5ns slope at 50% threshold, 355 ns
tΔBit(Bus) Transmitted bit width variation Bus recessive bit length variation relative to TxD bit length, tΔBit(Bus) = tBit(Bus) - tBit(TXD)
45Ω ≤ RL ≤ 65Ω; See Figure 9-6		 –10 10 ns
tΔBIT(RxD) Received bit width variation RxD recessive bit length variation relative to TXD bit length, tΔBit(RxD) = tBit(RXD) - tBit(TXD)
45Ω ≤ RL ≤ 65Ω; See Figure 9-6		 –30 20 ns
tΔREC Receiver timing symmetry RXD recessive bit length variation relative to bus bit length, tΔREC = tBit(RXD) - tBit(Bus) 45Ω ≤ RL ≤ 65Ω; See Figure 9-6 –20 15 ns
SPI SWITCHING CHARACTERISTICS
fSCK SCK, SPI clock frequency Normal, standby, listen and  failsafe modes 4 MHz
Sleep mode: If VIO is present 10 kHz
tSCK SCK, SPI clock period Normal, standby, listen and  failsafe modes; see Figure 9-11 250 ns
Sleep mode: If If VIO is present; See Figure 9-11 100 µs
tRSCK SCK rise time See Figure 9-10 40 ns
tFSCK SCK fall time See Figure 9-10 40 ns
tSCKH SCK, SPI clock high Normal, standby, listen and  failsafe modes; see Figure 9-11 125 ns
Sleep mode: If VIO is present; See Figure 9-11 500 ns
tSCKL SCK, SPI clock low Normal, standby, listen and  failsafe modes; see Figure 9-11 125 ns
Sleep mode: If VIO is present 500 ns
tCSS Chip select setup time See Figure 9-10 100 ns
tCSH Chip select hold time See Figure 9-10 100 ns
tCSD Chip select disable time See Figure 9-10 50 ns
tSISU Data in setup time Normal, standby, listen and  failsafe modes; see Figure 9-10 50 ns
Sleep mode: If VIO is present; see Figure 9-10 200 ns
tSIH Data in hold time Normal, standby, listen and  failsafe modes; see Figure 9-10 50 ns
Sleep mode: If VIO is present; see Figure 9-10 200 ns
tSOV Data out valid Normal, standby, listen and  failsafe modes; see Figure 9-11 80 ns
Sleep mode: If VIO is present; see Figure 9-11 200 ns
tRSO Data out rise time See Figure 9-11 40 ns
tFSO Data out fall time See Figure 9-11 40 ns