SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RSVD | |||||||
R | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RSVD | |||||||
R | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NISO | TXP | EFBI | PXHD | RSVD | BRSE | FDOE | |
RP | RP | RP | RP | R | RP | RP | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TEST | DAR | MON | CSR | CSA | ASM | CCE | INIT |
Rp | RP | Rp | R/W | R | Rp | RP | R/W |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:24 | RSVD | R | 0x0 | Reserved |
23:16 | RSVD | R | 0x0 | Reserved |
15 | NISO | RP | 0 | Non-ISO Operation 0 – CAN FD Frame format according to ISO 11898-1:2015 1 – CAN FD Frame format according to Bosch CAN FD Specification V1.0 |
14 | TXP | RP | 0 | Transmitter Pause 0 – Transmitter Pause Disabled 1 – Transmitter Pause Enabled |
13 | EFBI | RP | 0 | Edge Filtering during Bus Integration 0 – Edge Filtering Disabled 1 – Two Consecutive Dominant tq required to detect an edge for hard synchronization |
12 | PXHD | RP | 0 | Protocol Exception Handling Disable 0 – Protocol Exception Handling Enabled 1 – Protocol Exception Handling Disabled |
11:10 | RSVD | R | 0x0 | Reserved |
9 | BRSE | RP | 0 | Bit Rate Switch Enable 0 – Bit Rate Switching for Transmission Disabled 1 – Bit Rate Switching for Transmission Enabled |
8 | FDOE | RP | 0 | FD Operation Enable 0 – FD Operation Disabled 1 – FD Operation Enabled |
7 | TEST | Rp | 0 | Test Mode Enable 0 – Normal Mode of Operation, Register TEST Holds Reset Value 1 – Test Mode, Write Access to Register TEST Enabled |
6 | DAR | RP | 0 | Disable Automatic Retransmission 0 – Automatic Retransmission of Messages not Transmitted Successfully Enabled 1 – Automatic Retransmission Disabled |
5 | MON | Rp | 0 | Bus Monitoring Mode is Disabled 0 – Bus Monitoring Mode is Disabled 1 – Bus Monitoring Mode is Enabled |
4 | CSR | R/W | 1 | Clock Stop Request 0 – No clock Stop is requested 1 – Clock Stop Requested. When requested first INIT and then CSA will be set after all pending transfer request have completed and the CAN bus reached idle See NOTE section |
3 | CSA | R | 1 | Clock Stop Acknowledge 0 – No Clock Stop Requested 1 – m_can may be set in power down by stopping m_can-hclk and m_can_cclk |
2 | ASM | Rp | 0 | Restricted Operation Mode 0 – Normal CAN Operation 1 – Restricted Operation Mode Active |
1 | CCE | RP | 0 | Configuration Change Enable 0 – CPU has no write access to the protected configuration registers 1 – CPU has write access to the protected configuration registers (While CCCR.INIT =1) |
0 | INIT | R/W | 1 | Initialization 0 – Normal Operation 1 – Initialization has started |
The TCAN4550-Q1 handles stop request through hardware. The means that a 1 should not be written to CCCR.CSR (Clock Stop Request) as this will interfere with normal operation. If a Read-Modify-Write operation is performed in Standby mode a CSR = 1 will be read back but a 0 should be written to it.