SLLSFG3 May   2020 THVD1428

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC Specifications
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Dissipation
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Electrostatic Discharge (ESD) Protection
      2. 8.3.2 Electrical Fast Transient (EFT) Protection
      3. 8.3.3 Surge Protection
      4. 8.3.4 Failsafe Receiver
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver: THVD1428
tr, tf Differential output rise / fall time RL = 54 Ω, CL = 50 pF, see Figure 9 9 16 ns
tPHL, tPLH Propagation delay 12 25 ns
tSK(P) Pulse skew, |tPHL – tPLH| 6 ns
tPHZ, tPLZ Disable time 18 40 ns
tPZH, tPZL Enable time RE = 0 V, see Figure 10 and Figure 11 16 40 ns
RE = VCC, see Figure 10 and Figure 11 2.8 11 µs
Receiver: THVD1428
tr, tf Output rise / fall time CL = 15 pF, see Figure 12 2 6 ns
tPHL, tPLH Propagation delay 12 45 ns
tSK(P) Pulse skew, |tPHL – tPLH| 6 ns
tPHZ, tPLZ Disable time 14 28 ns
tPZH(1), tPZL(1), tPZH(2), tPZL(2), Enable time DE = VCC, see Figure 13 75 110 ns
DE = 0 V, see Figure 14 4.8 14 µs