SLFS043J August   1983  – November 2023 TLC555

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
    6. 5.6 Electrical Characteristics: VDD = 5 V
    7. 5.7 Electrical Characteristics: VDD = 15 V
    8. 5.8 Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Monostable Operation
      2. 6.3.2 Astable Operation
      3. 6.3.3 Frequency Divider
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Missing-Pulse Detector
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Pulse-Width Modulation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 Pulse-Position Modulation
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curves
      4. 7.2.4 Sequential Timer
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
        3. 7.2.4.3 Application Curve
      5. 7.2.5 Designing for Improved ESD Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • PS|8
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-E2696931-FECA-479C-901E-5B7FC1FCEFBF-low.gifFigure 4-1 D, P, PS, and JG Packages, 8-Pin SOIC, PDIP, SOP, and CDIP (Top View)
Table 4-1 Pin Functions: D, P, PS, and JG Packages
PIN TYPE DESCRIPTION
NAME NO.
CONT 5 Input Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
DISCH 7 Output Open collector output to discharge timing capacitor.
GND 1 — Ground.
NC — — No internal connection.
OUT 3 Output High current timer output signal.
RESET 4 Input Active low reset input forces output and discharge low.
THRES 6 Input End of timing input. THRES > CONT sets output low and discharge low.
TRIG 2 Input Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
VDD 8 — Power-supply voltage.
GUID-D27BA013-BB80-423F-BAC2-1D64082DF8DA-low.gifFigure 4-2 PW Package, 14-Pin TSSOP (Top View)
GUID-AE054ADE-63B3-4E97-B0F6-A7A6B05B84D8-low.gifFigure 4-3 FK Package, 20-Pin LCCC (Top View)
Table 4-2 Pin Functions: PW and FK
PIN TYPE DESCRIPTION
NAME NO.
PW (TSSOP) FK (LCCC)
CONT 8 12 Input Controls comparator thresholds. Outputs 2/3 VDD and allows bypass capacitor connection.
DISCH 12 17 Output Open-collector output to discharge timing capacitor.
GND 1 2 — Ground.
NC 2, 4, 6,
9, 11, 13		 1, 3, 4, 6, 8,
9, 11, 13, 14, 16, 18, 19		 — No internal connection.
OUT 5 7 Output High current timer output signal.
RESET 7 10 Input Active low reset input forces output and discharge low.
THRES 10 15 Input End of timing input. THRES > CONT sets output low and discharge low.
TRIG 3 5 Input Start of timing input. TRIG < 1/2 CONT sets output high and discharge open.
VDD 14 20 — Power-supply voltage.