SCLS711A March   2009  – November 2015 TLC59210

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VCC = 4.5 V to 5.5 V
    6. 6.6  Electrical Characteristics: VCC = 3 V to 3.6 V
    7. 6.7  Timing Requirements: VCC = 4.5 V to 5.5 V
    8. 6.8  Timing Requirements: VCC = 3 V to 3.6 V
    9. 6.9  Switching Characteristics: VCC = 4.5 V to 5.5 V
    10. 6.10 Switching Characteristics: VCC = 3 V to 3.6 V
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Setting LED Current
      2. 9.1.2 PWM Brightness Dimming
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The TLC59210 is an 8-bit flip-flop driver for LED and solenoid with Schmitt-trigger buffers. Each output channel is controlled by a positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) input meeting the setup time requirements is transferred to the Y output on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

8.2 Functional Block Diagram

TLC59210 outschem_cls711.gif Figure 6. Output Schematic
TLC59210 bd_cls711.gif
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
Figure 7. Logic Symbol

8.3 Feature Description

The TLC59210 features the ability to independently control 8 Sinking Outputs (Y). At each CLK pulse the output can be latched high or low depending on the input state (D). The CLR function allows for all outputs to be set high.

8.4 Device Functional Modes

Table 1. Function Table
(Each Latch)(1)

INPUTS OUTPUT
Y
CLR CLK D
L X X H*
H ↑ L H*
H ↑ H L
H L X Y0
H ↓ X Y0
(1) L: Low-level, H: High-level, H*: with pullup resistor, X: Irrelevant, ↑: Rising edge,↓: Falling edge, Z : High-impedance (OFF)