9.3.1 Thermal-Shutdown and Thermal-Error Flags

The thermal shutdown (TSD) function turns off all constant-current outputs on the device when the junction temperature (T_J) exceeds the threshold (T_TEF = 163°C, typ) and sets the thermal error flag (TEF) to 1. All outputs are latched off when TEF is set to 1 and remain off until the next grayscale cycle after XBLNK goes high and the junction temperature drops below (T_TEF – T_HYST). TEF remains as 1 until GSLAT is input with low temperature. TEF is set to 0 once the junction temperature drops below (T_TEF – T_HYST), but the output does not turn on until the first GSCKR, -G, or -B in the next display period even if TEF is set to 0.

1. An internal signal also works to turn the constant outputs, the same as the XBLNK input. The internal blank signal is generated at the rising edge of the GSLAT input signal for GS data with the display-timing reset enabled. Also, the signal is generated at the 4096th GSCKR, -G, or -B when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 41. TEF and TSD Timing

9.3.2 Noise Reduction

Large surge currents may flow through the device and the board on which the device is mounted if all 24 outputs turn on simultaneously at the start of each grayscale cycle. These large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5951 device turns the outputs on in a series delay for each group independently to provide a circuit soft-start feature. The output current sinks are grouped into four groups in each color group. For example, for the RED color output, the first grouped outputs that are turned on or off are OUTR0 and OUTR4. The second grouped outputs that are turned on or off are OUTR1 and OUTR5. The third grouped outputs are OUTR2 and OUTR6, and the fourth grouped outputs are OUTR3 and OUTR7. Each grouped output is turned on and off sequentially with a small delay between groups. However, each color output on and off is controlled by the color grayscale clock.

9.4.1 Maximum Constant Sink-Current Value

The TLC5951 maximum constant sink-current value for each channel, I_OLCMax, is determined by an external resistor, R_IREF, placed between R_IREF and GND. The R_IREF resistor value is calculated with Equation 1.

Equation 1.

where

• V_IREF = the internal reference voltage on IREF (1.2 V, typically)

I_OLCMax is the largest current for each output. Each output sinks the I_OLCMax current when it is turned on, the dot correction is set to the maximum value of 7Fh (127d), and the global brightness control data are set to the maximum value of FFh (255d). Each output sink current can be reduced by lowering the output dot correction or brightness control value.

R_IREF must be between 1.2 kΩ and 24 kΩ to keep I_OLCMax between 40 mA (typ) and 2mA (typ); the output may be unstable when I_OLCMax is set lower than 2 mA. Output currents lower than 2 mA can be achieved by setting I_OLCMax to 2 mA or higher and then using dot correction and global brightness control to lower the output current.

Figure 7 and Table 1 show the constant sink current versus external resistor, R_IREF, characteristics. Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each output.

9.4.2 Dot Correction (DC) Function

The TLC5951 device has the capability to adjust the output current of each channel (OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7) individually. This function is called dot correction (DC). The DC function allows the brightness and color deviations of LEDs connected to each output to be individually adjusted. Each output DC is programmed with a 7-bit word for each channel output. Each channel output current is adjusted in 128 steps within one of two adjustment ranges. The dot-correction high-adjustment range allows the output current to be adjusted from 33.3% to 100% of the maximum output current, I_OLCMax. The dot-correction-low adjustment range allows the output current to be adjusted from 0% to 66.7% of I_OLCMax. The range control bits in the function control latch select the high or low adjustment range. Equation 2 and Equation 3 calculate the actual output current as a function of R_IREF, DC value, adjustment range, and brightness control value. There are three range control bits that control the DC adjustment range for three groups of outputs: OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7. DC data are programmed into the TLC5951 device via the serial interface.

When the device is powered on, the DC data in the 216-bit common shift register and data latch contain random data. Therefore, DC data must be written to the DC latch before turning the constant-current output on. Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.

9.4.3 Global Brightness Control (BC) Function

The TLC5951 device has the capability to adjust the output current of each color group simultaneously. This function is called global brightness control (BC). The global brightness control for each of the three color groups, (OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7), is programmed with a separate 8-bit word. The BC of each group is adjusted with 256 steps from 0% to 100%. 0% corresponds to 0 mA. 100% corresponds to the maximum output current programmed by R_IREF and each output DC value. Note that even though the BC values for all color groups are identical, the output currents can be different if the DC values are different. Equation 2 and Equation 3 calculates the actual output current as a function of R_IREF, the DC adjustment range, and the brightness control value. BC data are programmed into the TLC5951 device via the serial interface.

When the device is powered on, the BC data in the 216-bit common shift register and data latch contain random data. Therefore, BC data must be written to the BC latch before turning the constant-current output on. Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.

Equation 2 determines the output sink current for each color group when the dot-correction high-adjustment range is chosen.

Equation 2.

Equation 3 determines the output sink current for each color group when the dot-correction low-adjustment range is chosen.

Equation 3.

where

• I_OLCMax = the maximum channel current for each channel determined by R_IREF
• DC = the decimal dot correction value for the output. This value ranges between 0 and 127.
• BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.

9.4.4 Grayscale (GS) Function (PWM Control)

The TLC5951 device can adjust the brightness of each output channel using a pulse width modulation (PWM) control scheme. The use of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness. The grayscale circuitry is duplicated for each of the three color groups.

The PWM operation for each color group is controlled by a 12-bit GS counter. Three GS counters are implemented to control each of the three color outputs, OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7. Each counter increments on each rising edge of the grayscale reference clock (GSCKR, GSCKG, or GSCKB). The falling edge of XBLNK resets the three counter values to 0. The grayscale counter values are held at 0 while XBLNK is low, even if the GS clock input is toggled high and low. Pulling XBLNK high enables the GS clock. The first rising edge of a GS clock after XBLNK goes high increments the corresponding grayscale counter by one and switches on all outputs with a non-zero GS value programmed into the GS latch. Each additional rising edge on a GS clock increases the corresponding GS counter by one.

The GS counters keep track of the number of clock pulses from the respective GS clock inputs (GSCKR, GSCKG, and GSCKB). Each output stays on while the counter is less than or equal to the programmed grayscale value. Each output turns off at the rising edge of the GS counter value when the counter is larger than the output grayscale latch value.

Equation 4 calculates each output (OUTRn, -Gn, -Bn) on-time (t_{OUT_ON}):

Equation 4.

where

• I_OLCMax = the maximum channel current for each channel determined by R_IREF
• DC = the decimal dot correction value for the output. This value ranges between 0 and 127.
• BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.

When new GS data are latched into the GS data latch with the rising edge on GSLAT during a PWM cycle, the GS data latch registers are immediately updated. This latching can cause the outputs to turn on or off unexpectedly. For proper operation, GS data should only be latched into the device at the end of a display period when XBLNK is low. Table 6 summarizes the GS data value versus the output on-time duty cycle.

When the device is powered up, the 288-bit common shift register and GS data latch contain random data. Therefore, GS data must be written to the GS latch before turning the constant-current output on. Additionally, XBLNK should be low when the device is powered up to prevent the outputs from turning on before the proper GS values are programmed into the registers. All constant-current outputs are off when XBLNK is low.

If there are any unconnected outputs (OUTRn, OUTGn, and OUTBn), including LEDs in a failed short or failed open condition, the GS data corresponding to the unconnected output should be set to 0 before turning on the LEDs. Otherwise, the VCC supply current (I_VCC) increases while that constant-current output is programmed to be on.

9.4.4.1 PWM Counter 12-Bit Mode Without Auto Repeat

1. The internal blank signal is generated at the rising edge of the GSLAT input signal for GS data with the display-timing reset enabled. Also, the signal is generated at the 4096th GSCKR, -G, or -B when the auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 42. PWM Operation 1

9.4.4.2 PWM Counter 8-, 10-, or 12-Bit Mode Without Auto Repeat

Figure 43. PWM Operation 2

9.4.4.3 PWM Counter 8-, 10-, or 12-Bit Mode With Auto Repeat

Figure 44. PWM Operation 3

9.4.5 Register and Data Latch Configuration

The TLC5951 device has two data latches to store information: the grayscale (GS) data latch and the DC, BC, FC, and UD data latch. The GS data latch can be written as 288-bit data through GSSIN with GSSCK. The DC, BC, FC, and UD data latch can be written as data through DCSIN with DCSCK. Also, DC, BC, and FC data can be written to the DC, BC, FC, and UD data latch through GSSIN with GSSCK. UD data are written to the upper 17 bits of the 216-bit DC, BC, FC, and UD shift register at the same time. The data in the DC, BC, FC, and UD data latch can be read via GSSOUT with GSSCK. Figure 45 shows the grayscale shift register and data latch configuration.

Figure 45. Grayscale Shift Register and Data Latch Configuration

9.4.5.2 Grayscale Data Latch

The grayscale (GS) data latch is 288 bits long. This latch contains the 12-bit PWM grayscale value for each of the TLC5951 constant-current outputs. The PWM grayscale values in this latch set the PWM on-time for each constant-current driver. See Table 6 for the on-time duty of each GS data bit. Figure 46 shows the shift register and latch configuration. Refer to Figure 3 for the timing diagram for writing data into the GS shift register and latch.

Data are latched from the 288-bit common shift register into the GS data latch at the rising edge of the GSLAT pin. The conditions for latching data into this register are described in the 288-Bit Common Shift Register section. When data are latched into the GS data latch, the new data are immediately available on the constant-current outputs. For this reason, data should only be latched when XBLNK is low. If data are latched with XBLNK high, the outputs may turn on or off unexpectedly.

Figure 46. Grayscale Data-Latch Configuration

When the IC powers on, the grayscale data latch contains random data. Therefore, grayscale data must be written to the 288-bit common shift register and latched into the GS data latch before turning on the constant-current outputs. XBLNK should be low when powering on the TLC5951 to force all outputs off until the internal registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in Table 7.

Table 7. Grayscale Data-Bit Assignment

BITS	DATA		BITS	DATA
11–0	OUTR0		155–144	OUTR4
23–12	OUTG0		167–156	OUTG4
35–24	OUTB0		179–168	OUTB4
47–36	OUTR1		191–180	OUTR5
59–48	OUTG1		203–192	OUTG5
71–60	OUTB1		215–204	OUTB5
83–72	OUTR2		227–216	OUTR6
95–84	OUTG2		239–228	OUTG6
107–96	OUTB2		251–240	OUTB6
119–108	OUTR3		263–252	OUTR7
131–120	OUTG3		275–264	OUTG7
143–132	OUTB3		287–276	OUTB7

9.4.5.3 DC, BC, FC, and UD Shift Register

The 216-bit DC, BC, FC, and UD shift register is used to shift data from the DSSIN pin into the TLC5951 device. The data shifted into this register are used for the dot correction (DC), global brightness control (BC), function control (FC), and user-defined (UD) data latches. Each of these latches is described in the following sections. The register LSB is connected to DCSIN and the MSB is connected to DCSOUT. On each DCSCK rising edge, the data on DCSIN are shifted into the register LSB and all 216 bits are shifted towards the MSB. The register MSB is always connected to DCOUT. When the device is powered on, the 216-bit DC, BC, FC, and UD shift register contains random data.

9.4.5.3.1 DC, BC, FC, and UD Data Latch

The 216-bit DC, BC, FC, and UD data latch contains dot correction (DC) data, global brightness control (BC) data, function control (FC) data, and user-defined (UD) data. Data can be written into this latch from the DC, BC, FC, and UD shift register. Furthermore, DC, BC, and FC data can be written into this latch from the 288-bit common shift register. At this time, UD data are written to bits 199–215 in the 216-bit DC, BC, FC, and UD shift register data latch. When the IC is powered on, the DC, BC, FC, and UD data latch contains random data.

Figure 47. DC, BC, FC, and UD Data–Latch Configuration

9.4.5.3.2 Dot–Correction Data Latch

The dot correction (DC) data latch is 168 bits long. The DC data latch consists of bits 0–167 in the DC, BC, FC, and UD data latch. This latch contains the 7–bit DC value for each of the TLC5951 constant–current outputs. Each DC value individually adjusts the output current for each constant–current driver. As explained in the Dot Correction (DC) Function section, the DC values are used to adjust the output current from 0% to 66.7% of the maximum value when the dot correction low adjustment range is selected and from 33.3% to 100% of the maximum value when the dot correction high adjustment range is selected. The adjustment range is selected by the range control bits in the function control latch.

Table 2 and Table 3 show how the DC data affect the percentage of the maximum current for each output. See Figure 47 for the DC data latch configuration. Figure 4 illustrates the timing diagram for writing data from the GS data path into the shift registers and latches. Figure 5 illustrates the timing diagram for writing data from the DC data path into the shift registers and DC latches. DC data are automatically latched from the DC, BC, FC, and UD shift register into the DC data latch with an internal latch signal. The internal latch signal is generated in 3 ms to 7 ms after the last DCSCK rising edge.

When the device powers on, the DC data latch contains random data. Therefore, DC data must be written into the TLC5951 device and latched into the DC data latch before turning on the constant-current outputs. XBLNK should be low when powering on the TLC5951 device to force all outputs off until the internal registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in Table 8.

Table 8. Dot-Correction Data-Bit Assignment

BITS	DATA		BITS	DATA
6–0	OUTR0		90–84	OUTR4
13–7	OUTG0		97–91	OUTG4
20–14	OUTB0		104–98	OUTB4
27–21	OUTR1		111–105	OUTR5
34–28	OUTG1		118–112	OUTG5
41–35	OUTB1		125–119	OUTB5
48–42	OUTR2		132–126	OUTR6
55–49	OUTG2		139–133	OUTG6
62–56	OUTB2		146–140	OUTB6
69–63	OUTR3		153–147	OUTR7
76–70	OUTG3		160–154	OUTG7
83–77	OUTB3		167–161	OUTB7

9.4.5.3.3 Global-Brightness Control-Data Latch

The global brightness control (BC) data latch is 24 bits long. The BC data latch consists of bits 168–191 in the DC, BC, FC, and UD data latch.

The data of the BC data latch are used to adjust the constant-current values for eight channel constant-current drivers of each color group. The current can be adjusted from 0% to 100% of each output current adjusted by brightness control with 8-bit resolution. Table 4 describes the percentage of the maximum current for each brightness control data.

When the IC is powered on, the data in the BC data latch are not set to a specific default value. Therefore, brightness control data must be written to the BC latch before turning on the constant-current output. The data bit assignment is shown in Table 9.

Table 9. Data-Bit Assignment

BITS	GLOBAL BRIGHTNESS CONTROL DATA BITS 7–0
175–168	OUTR0–OUTR7 group
183–176	OUTG0–OUTG7 group
191–184	OUTB0–OUTB7 group

9.4.5.3.4 Function-Control Data Latch

The function control (FC) data latch is 7 bits in length and is used to select the dot-correction adjustment range, grayscale counter mode, enabling of the auto display repeat, and display timing reset function. When the device is powered on, the data in the FC latch are not set to a specific default value. Therefore, function control data must be written to the FC data latch before turning on the constant-current output.

Table 10. Data-Bit Assignment

BIT	DESCRIPTION
192	Dot correction adjustment range for the RED color output (0 = lower range, 1 = higher range). When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the red LED driver group. When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current set by an external resistor.
193	Dot correction adjustment range for the GREEN color output (0 = lower range, 1 = higher range). When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the green LED driver group. When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current set by an external resistor.
194	Dot correction adjustment range for the BLUE color output (0 = lower range, 1 = higher range). When this bit is 0, dot correction can control the range of constant current from 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the blue LED driver group. When this bit is 1, dot correction can control the range of constant current from 33.3% (typ) to 100% of the maximum current set by an external resistor.
195	Auto display repeat mode (0 = disabled, 1 = enabled). When this bit is 0, the auto repeat function is disabled. Each output driver is turned on and off once after XBLNK goes high. When this bit is 1, each output driver is repeatedly toggled on and off every 4096th grayscale clock without the XBLNK level changing when the GS counter is configured in the 12-bit mode. If the GS counter is configured in the 10-bit mode, the outputs continue to cycle on and off every 1024th grayscale clock. If the GS counter is set to the 8-bit mode, the output on-off repetition cycles every 256th grayscale clock.
196	Display timing reset mode (0 = disabled, 1 = enabled). When this bit is 1, the GS counter is reset to 0 and all outputs are forced off at the GSLAT rising edge for a GS data write. This function is identical to the low pulse of the XBLNK signal when input. Therefore, the XBLNK signal is not needed to control from a display controller. PWM control starts again from the next input GSCKR, -G, or -B rising edge. When this bit is 0, the GS counter is not reset and no outputs are forced off even if a GSLAT rising edge is input. In this mode, the XBLNK signal should be input after the PWM control of all LEDs is finished. Otherwise, the PWM control might be not exact.
198, 197	Grayscale counter mode select, bits 1–0. The grayscale counter mode is selected by the setting of bits 1 and 0. Table 11 shows the GS counter mode.

Table 11. GS Counter-Mode Truth Table

GRAYSCALE COUNTER MODE		FUNCTION MODE
BIT 1	BIT 0
0	X (don't care)	12-bit counter mode (maximum output on-time = 4095 × GS clock)
1	0	10-bit counter mode (maximum output on-time = 1023 × GS clock)
1	1	8-bit counter mode (maximum output on-time = 255 × GS clock)

The grayscale data latch bit length is always 288 bits in any grayscale counter mode. All constant-current outputs are forced off at the 256th grayscale clock in the 8-bit mode even if all grayscale data are FFFh. In 10-bit mode, all outputs are forced off at 1024th grayscale clock even if all grayscale data are FFFh.

9.4.5.3.5 User-Defined Data Latch

The user-defined (UD) data latch is 17 bits in length and is not used for any device functionality. However, these data can be used for communication between a controller connected to DCSIN and another controller connected to GSSIN. When the device is powered on, the data in the UD latch are not set to a specific default value.

Table 12. Data-Bit Assignment

BITS	USER-DEFINED DATA BITS
215–199	16–0

9.4.6 Status Information Data (SID)

Status information data (SID) are 288 bits in length and are read-only data. SID consists of the LED open-detection (LOD) error, LED short-detection (LSD), thermal-error flag (TEF), and the data in the DC, BC, FC, and UD data latch. The SID are shifted out onto GSSOUT with the GSSCK rising edge after GSLAT is input for a GS data write. These SID are loaded into the 288-bit common shift register after data in the 288-bit common shift register are copied to the data latch.

Figure 48. DC, BC, and FC Data-Load Assignment

9.4.7 Continuous Base LOD, LSD, and TEF

The LOD and LSD data are updated at the rising edge of the 33rd GSCKR, -G, or -B pulse after XBLNK goes high and the data are retained until the next 33rd GSCKR, -G, or -B. LOD and LSD data are valid when GS data are equal to or higher than 20h (32d). If GS data are less than 20h (32d), LOD and LSD data are not valid and must be ignored. A 1 in an LOD bit indicates an open LED or shorted LED to GND with a low-impedance condition for the corresponding output. A 0 indicates normal operation. A 1 in an LSD bit indicates a shorted LED condition for the corresponding output. A 0 indicates normal operation. When the device is powered on, LOD and LSD data do not show correct values. Therefore, LOD and LSD data must be read from the 33rd GSCKR, -G, or -B pulse input after XBLNK goes high.

The TEF bit indicates that the device temperature is too high. The TEF flag also indicates that the device has turned off all drivers to avoid damage by overheating the device. A 1 in the TEF bit means that the device temperature has exceeded the detect temperature threshold (T_TEF) and all outputs are turned off. A 0 in the TEF bit indicates normal operation with normal temperature conditions. The device automatically turns the drivers back on when the device temperature decreases to less than (T_TEF – T_HYST). Table 14 shows a truth table for LOD, LSD, and TEF.

1. The internal blank signal is generated at the rising edge of the GSLAT input signal for GS data with the display-timing reset enabled. Also, the signal is generated at the 4096th GSCK when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 49. LED-Open Detection (LOD), LED-Shorted Detection, and Data-Update Timing