SLAS715C June   2010  – January 2023 TLV320AIC3104-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 8.8  Switching Characteristics DSP Timing in Master Mode
    9. 8.9  Switching Characteristics DSP Timing in Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing for Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio DAC
      8. 9.3.8  Audio DAC Digital Volume Control
      9. 9.3.9  Analog Output Common-mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High-Power Output Drivers
      18. 9.3.18 Short-Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing for Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Power Down
      4. 9.4.4 Hardware Reset
    5. 9.5 Programming
      1. 9.5.1  Digital Control Serial Interface
      2. 9.5.2  I2C Control Interface
      3. 9.5.3  I2C Bus Debug in a Glitched System
      4. 9.5.4  Digital Audio Data Serial Interface
      5. 9.5.5  Right-Justified Mode
      6. 9.5.6  Left-Justified Mode
      7. 9.5.7  I2S Mode
      8. 9.5.8  DSP Mode
      9. 9.5.9  TDM Data Transfer
      10. 9.5.10 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.7 Delta-Sigma Audio DAC

The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a continuous-time RC filter. The analog FIR operates at a rate of 128 fS(ref) (6.144 MHz when fS(ref) = 48 kHz, 5.6448 MHz when fS(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.