SBOSA91B December   2021  – December 2023 TLV2387 , TLV387 , TLV4387

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: TLV387
    5. 5.5 Thermal Information: TLV2387
    6. 5.6 Thermal Information: TLV4387
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Bias Current
      2. 6.3.2 EMI Susceptibility and Input Filtering
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Load Cell Measurement
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, VS = ±2.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 50 pF (unless otherwise noted)

GUID-20201027-CA0I-5CK4-CZBG-KCCBFTW1ZMNF-low.gif
 VS = 5.5 V
Figure 5-1 Offset Voltage Drift Distribution
GUID-20201027-CA0I-SBGJ-6F4L-PCPL3MGSTXDL-low.gif
 
Figure 5-3 Offset Voltage vs Common-Mode Voltage
GUID-20201027-CA0I-1TBK-HND0-WWM4RPZSB5JM-low.gif
 
Figure 5-5 Open-Loop Gain and Phase vs Frequency
GUID-20201027-CA0I-CWKG-VPJW-LTHFT8RHLPHL-low.gif
 
Figure 5-7 Closed-Loop Gain and Phase vs Frequency
GUID-20201203-CA0I-ZNZF-TQJ0-S3GNRBWTRHHX-low.gif
 
Figure 5-9 CMRR vs Temperature
GUID-20201203-CA0I-6TQK-JX4L-K0QQ3GDMN4X1-low.gif
 
Figure 5-11 0.1-Hz to 10-Hz Noise
GUID-20201203-CA0I-DQQL-GGWR-CHPN93JTJNJ7-low.gif
 
Figure 5-13 Channel-to-Channel Crosstalk
GUID-20201203-CA0I-LKCR-P8V0-JFHCXPNSRH9Z-low.gif
VS = 5.5 V, f = 1 kHz, BW = 80 kHz
 
Figure 5-15 THD+N vs Output Amplitude
GUID-20201027-CA0I-LJTP-NF5B-MVKVW20TWL8W-low.gif
 
Figure 5-17 Quiescent Current vs Temperature
GUID-20201203-CA0I-1VJJ-SWK9-Q1SFZMRHJSD8-low.gif
G = –1, 10 mV step
Figure 5-19 Small-Signal Overshoot vs Capacitive Load
GUID-20201203-CA0I-PRMK-SCRS-FC3MNQMBH1F6-low.gif
 
Figure 5-21 Phase Margin vs Capacitive Load
GUID-20201203-CA0I-VDXH-GZHB-RNXKF3FGP5P5-low.gif
G = –1
Figure 5-23 Overload Recovery
GUID-20201027-CA0I-00C7-HGTC-XNKHQH1DMNGJ-low.gif
 
Figure 5-25 Large-Signal Step Response (4-V Step)
GUID-20201027-CA0I-645V-N8XH-2CDTWBK6FLKS-low.gif
 
Figure 5-2 Offset Voltage vs Temperature
GUID-20201027-CA0I-8ZD9-8MDH-PSST3ZFHTDT3-low.gif
 
Figure 5-4 Offset Voltage vs Supply Voltage
GUID-20201203-CA0I-3D0P-V1KZ-2WKB1KX5QNKF-low.gif
 
Figure 5-6 Open-Loop Gain vs Temperature
GUID-20210813-SS0I-ZXKV-M0XD-GDST4HWNRZC9-low.svg
 
Figure 5-8 Input Bias Current vs Common-Mode Voltage
GUID-20201203-CA0I-NLKT-XSZ5-CZ4G2NHRK1V6-low.gif
 
Figure 5-10 PSRR and CMRR vs Frequency
GUID-20201027-CA0I-JVK5-LV1D-PTJDPGQMLHCD-low.gif
 
Figure 5-12 Input Voltage Noise Spectral Density vs Frequency
GUID-20201203-CA0I-T0M1-RJCH-KL22Q60RW0X7-low.gif
VS = 5.5 V, VOUT = 3 VRMS, BW = 80 kHz
 
Figure 5-14 THD+N Ratio vs Frequency
GUID-20201027-CA0I-214T-V8LR-9RRFDJLZZBXP-low.gif
 
Figure 5-16 Quiescent Current vs Supply Voltage
GUID-20201203-CA0I-ZVGW-KPJQ-DGH4JBK1XH1J-low.gif
 
Figure 5-18 Open-Loop Output Impedance vs Frequency
GUID-20201203-CA0I-MH0H-FNM5-RZTQQP7DGVKT-low.gif
G = +1, 10 mV step
Figure 5-20 Small-Signal Overshoot vs Capacitive Load
GUID-20201203-CA0I-FML7-3L1K-SNGDFFQPZLRB-low.gif
 
Figure 5-22 No Phase Reversal
GUID-20201203-CA0I-QZ7B-NCLD-6XQDBXZMBCWC-low.gif
G = +1
Figure 5-24 Small-Signal Step Response
GUID-20201203-CA0I-62HR-RQSG-RTKL6SRBLRB4-low.gif
0.01% settling = ±100 µV
Figure 5-26 Settling Time