SLOS907C April   2015  – December 2017 TPA3144D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Gain Setting via GAIN Pin
      2. 9.3.2  SD Operation
      3. 9.3.3  Gain Limit Control, LIMTHRES and LIMRATE
      4. 9.3.4  SPEAKERGUARD Automatic Gain Limit, AGL
      5. 9.3.5  Thermal Foldback, TFB
      6. 9.3.6  PLIMIT
      7. 9.3.7  LIMTHRES
      8. 9.3.8  Spread Spectrum and De-Phase Control
      9. 9.3.9  GVDD Supply
      10. 9.3.10 DC Detect
      11. 9.3.11 PBTL Select
      12. 9.3.12 Short-Circuit Protection and Automatic Recovery Feature
      13. 9.3.13 Thermal Protection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 PCB Material Recommendation
        2. 10.2.1.2 PVCC Capacitor Recommendation
        3. 10.2.1.3 Decoupling Capacitor Recommendations
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Ferrite Bead Filter Considerations
        2. 10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
        3. 10.2.2.3 When to Use an Output Filter for EMI Suppression
        4. 10.2.2.4 Input Resistance
        5. 10.2.2.5 Input Capacitor, Ci
        6. 10.2.2.6 BSN and BSP Capacitors
        7. 10.2.2.7 Differential Inputs
        8. 10.2.2.8 Using Low-ESR Capacitors
      3. 10.2.3 Application Performance Curves
        1. 10.2.3.1 EN55013 Radiated Emissions Results
        2. 10.2.3.2 EN55022 Conducted Emissions Results
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling, CS
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Gain Setting via GAIN Pin

The gain of the TPA3144D2 is set by a voltage applied to the GAIN pin, which is set by a resistor voltage divider with GVDD as supply voltage. The resistance of the voltage divider should be a minimum of 100 kΩ in order not to overload the GVDD regulator of TPA3144D2.

TPA3144D2 GAIN.gifFigure 16. GAIN Pin Voltage Programming by GVDD Resistor Divider

The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (Zi) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. The selected input gain is latched at device start up and cannot be changed when SD is high.

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3144D2. At the lower gain settings, the input impedance could increase as high as 72 kΩ.

Table 1. Gain Setting

GAIN PIN VOLTAGE AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ)
TYP TYP
0 V (GND) 20 60
2.3 V (1/3·GVDD) 26 30
4.6 V (2/3·GVDD) 32 15
6.9 V (GVDD) 36 9